When AP is off, turn off pullup on NSS, and set MISO to an input so
the SPI module won't drive it high if the last sent bit was a 1. This
reduces leakage when the AP is off.
This patch also fixes a bug where gpio_set_alternate_function() set
the wrong pins to normal-mode when func=-1; that didn't hit anything
else because that functionality wasn't used on STM32 until now.
BUG=chrome-os-partner:19304
BRANCH=none
TEST=boot pit
On EC console, with AP on, 'rw 0x40020000' returns
read 0x40020000 = 0x6569aa20 <- must have 0x____aa__
Then 'apshutdown' and 'rw 0x40020000' returns
read 0x40020000 = 0x65690020 <- must have 0x____00__
The 'power on' and AP turns back on. At u-boot prompt,
'sspi 2:0 256 9f00000000' returns
FDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFEEC010001
(some number of 0xFD's followed by FEEC...) This shows SPI
functionality is restored when AP is powered back on, and not
just at init time.
Change-Id: Ia3cd3e0bc222dc663d635509918fa3d383fd7971
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/51182
Reviewed-by: Simon Glass <sjg@chromium.org>
The current lm4 pwm module was using board-specific
pins during this configuration. Move the implementation
of configure_fan_gpios() to the board-specific files
so that the pin configuration policy isn't a part of the
common infrastructure.
BUG=chrome-os-partner:19504
BRANCH=none
TEST=successfully booted slippy with backlight turning on in OS.
Change-Id: I325f1ac4639b4a78d8b860df7a8b688ca385b71b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/51471
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
When system is locked, the console is disabled. However, we need console
for debugging and testing. This CL uses a bit from back-up register to
indicate if the console should always be enabled. (This bit is currently
used by fake WP, which is removed in this CL.) With this, we can set
this bit with console command 'forceen 1' to ensure console is never
disabled.
To prevent device shipped in this state, the chip name is postfixed with
'-unsafe' so that the device is not able to pass HWID check.
BUG=chrome-os-partner:19293
TEST=Manual
BRANCH=spring
Change-Id: I88556e973ca542c1bdc27ba64988718291e01a26
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/51086
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Slippy uses UART2 instead of UART1 and so the EC needs
to be able to tolerate having the host use a different
interface. There are of course many ways to accomplish
that but this approach adds two config variables to specify
the host uart and the host uart irq.
The UART port setup is split out to allow them to be
configured separately rather than needing to be adjacent
in a for loop.
The interrupt functions were renamed (to ec and host) in
order to indicate which interface they are responsible for.
BUG=chrome-os-partner:19356
BRANCH=none
TEST=boot slippy and see host serial output
Change-Id: I1913ff3d650f329224c9654eee7bb7412fae5402
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50837
This commits the hacks made during board bringup. Bugs can be filed and
fixed based on this starting point.
BUG=chrome-os-partner:18825
BRANCH=slippy
TEST=manual
Try it and see.
Change-Id: Ia663eaf9a357633873b1b5d5cc6dbdda63513082
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50875
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The i2cdetect command on Linux likes to probe by doing a write of 0
bytes. Rather than always returning success because there was nothing
to write, let's actually implement this command.
At the moment we only implement for the stm32l. We also don't try to
implement the "read of 0" bytes since I don't think anyone uses that.
BUG=chrome-os-partner:18778
BRANCH=none
TEST=i2cdetect -y -a 20 now detects the right devices
Change-Id: Ia159ce9b8c957d5cd11f187f1a179ca5967bf96f
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50009
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
The STM32L manual has a whole section on i2c master reads and
describes the correct method for receiving exactly 2 bytes and more
than 2 bytes. We weren't following those instructions and thus larger
transfers weren't working.
BUG=chrome-os-partner:19265
BRANCH=none
TEST=i2cxfer r16 0x90 0
...doesn't fail
TEST=i2cxfer r 0x90 0
...doesn't fail
TEST=Use pydevi2c and test some commands:
>>> tps = I2CDevice(20, 0x48)
>>> [hex(x) for x in tps.Get(0, 20)]
['0x1e', '0x0', '0x3e', '0x0', '0x12', '0x20', '0x4b', '0xbf',
'0xff', '0xff', '0x20', '0x12', '0x1e', '0x1e', '0x1e', '0x1f',
'0x1f', '0x1f', '0x1f', '0x1f']
Change-Id: Ifaab6d8b700e099bcd9c374c70fca0983858ed3f
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50229
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Perviously we use uint32_t for this, but this doesn't compile for 64-bit
environment (and likely doesn't for 16-bit either.) Use uintptr_t so that
we don't get size mismatch errors.
BUG=chrome-os-partner:19257
TEST=Run host emulated tests
BRANCH=None
Change-Id: I3cd66a745fa171c41a5f142514284ec106586acb
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50358
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If an ADC read fails and EOC bit is somehow never set, we will be stuck
in the read function holding mutex lock forever, which is really bad.
Let's set a timeout for this.
BUG=chrome-os-partner:18997
TEST=Boot Spring. Check ADC works.
BRANCH=spring
Change-Id: I19b108326f34f380497606fe92eabfaf0a778bb4
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50338
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
There was an off-by-one error in bounds checking the reply. You could
trigger it with pydevi2c with:
>>> tps = I2CDevice(20, 0x48, force=True)
>>> tps.Get(0, 249)
The EC would show:
ASSERTION FAILURE 'msg_len < sizeof(out_msg)' in reply() at
chip/stm32/spi.c:184
BUG=chrome-os-partner:18778
BRANCH=none
TEST=Run the above commands and see no error.
Change-Id: I9789405a9d70c5dc3fa237504fea8f46a139386c
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50254
Reviewed-by: Simon Glass <sjg@chromium.org>
I've simplified the SPI module, since we only ever use SPI1 (and there
were already a number of places which assumed this was true).
Somewhere along the way I fixed a number of problems keeping the code
from compiling and working on STM32L. The code isn't currently used
anywhere else, but should still work there (that is, I don't think I
broke it working on STM32F if you re-enable it on some STM32F
platform).
BUG=chrome-os-partner:19073
BRANCH=none
TEST=from u-boot console, sspi 2:0 64 9f0000
u-boot prints: FDFDFDFDFDFDFDFD
ec prints: [193.740912 HC 0x9f][193.741141 HC err 1]
[sjg: gpio optimization back in for now]
[dianders: add comment as rspangler requested; update SOBs]
Change-Id: Ib9419403e4e44dadc1f17681e48401882cb49175
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49684
This is needed for non-volatile register emulation. Also, this can be
used to implement system jump or reset flags.
BUG=chrome-os-partner:19235
TEST=Run utils test. Check persistent storage file exists.
BRANCH=None
Change-Id: I699f95718ef6f5de6c3bbb4e37619ee015fb6c4a
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50313
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This is the first version of pthread-based RTOS emulator. With this, we
will be able to test high-level modules entirely on the host machine.
BUG=chrome-os-partner:19325
TEST='make runtests' and see tests passing.
BRANCH=None
Change-Id: I1f5fcd76aa84bdb46c7d35c5e60ae5d92fd3a319
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49954
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
I'll still need to decide what to do differently for Slippy, but for now
let's just identify the places where there will likely be a difference.
BUG=chrome-os-partner:18825
BRANCH=slippy
TEST=manual
Link still works.
Change-Id: I950f0e5356ccf9838f2140d853122235f884e34f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49931
1) Port needs to be open-drain. Missed this when porting from STM32F
because open-drain and alternate function are set in the same register
on STM32F and are different regs on STM32L.
2) Queue a stop condition if a transaction failed, so the clock goes
back high.
BUG=chrome-os-partner:18969
BRANCH=none
TEST=i2cscan finds both the PMU at 0x90 and the battery at 0x16
Change-Id: I708b925e4e30da9d5864b74641b1cbe90c9313fe
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49898
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This fixes a bug in ADC watchdog that sample sequence is not set before
enabling ADC watchdog. Also, current sample time isn't long enough for
some weakly driven net. This extends ADC sample time to 13.5 cycles.
BUG=chrome-os-partner:17928
TEST=Test with Toad cable and video dongle on Spring
BRANCH=spring
Change-Id: Iecdfd4aada4e974225a41144e213e92897f4797b
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49680
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
STM32L doesn't need the DMA-based workarounds needed by STM32F, since
the STM32L I2C block isn't broken. DMA adds a lot of code overhead
when transferring 2-3 bytes, and is implemented differently on STM32F
vs STM32L so it doesn't even work on STM32L
Add a simple polled I2C implementation for STM32L. This is not the
final implementation, which will use interrupts, but for now it works,
unlike the DMA-based version.
BUG=chrome-os-partner:18969
BRANCH=none
TEST=i2cscan on pit finds a device at 0x90
Change-Id: Ie2a6c9ac6f62b7fd3c35e313b4015e080d9f937a
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49555
Also moves the handy i2cscan command to i2c_common. The
platform-dependent interface is now i2c_xfer().
Still more to do in follow-up CLs; for example, i2c_read_string() has
platform-dependent implementation, and the i2c/i2cread console
commands aren't common yet.
BUG=chrome-os-partner:18969
BRANCH=none
TEST=i2cscan on link, spring
Change-Id: Ia53d57beaa157bece293a4262257e20b4107589e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49492
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Queue: Daniel Erat <derat@chromium.org>
Commit-Queue: Simon Glass <sjg@chromium.org>
LM4 doesn't have implementation of adc_read_all_channels(). Let's use
adc_read_channel() in this case.
BUG=chrome-os-partner:18598
TEST=Build stress test for link. See no error about
adc_read_all_channels() undefined.
BRANCH=None
Change-Id: I5b13384468667cbd17b83faab9f9d3fdc48de91d
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49589
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This will let us check the size of static array initializers.
Also moved this macro definition and ARRAY_SIZE into a new "tricks.h"
header, so that userspace utils can use it too.
BUG=none
BRANCH=none
TEST=manual
Built everything, tested on Link. Tried various assertions.
Change-Id: I612891108ea37dbca3572e0f25ab54a7bc0ed860
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49417
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Sadly, the existence of fans may not always imply the existence of keyboard
backlights.
BUG=chrome-os-partner:18825
BRANCH=slippy
TEST=manual
Use the Link EC console to make sure that both functions still behave.
faninfo
fanset 4400
faninfo
fanset 9999
faninfo
autofan
faninfo
fanduty 50
faninfo
fanduty 100
faninfo
autofan
kblight 0
kblight 100
kblight 50
kbligth 100
Change-Id: I2e07cd46c21bce2d0d4162275a8ea6ae40135e96
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49355
STM32L has 16KB RAM, so can use a bigger output buffer.
BUG=chrome-os-partner:18657
BRANCH=none
TEST=boot pit, look at EC console output; shouldn't drop output
Change-Id: I8a3c7ff2923fd815eff748a898dc873f5d86b46c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49332
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
We don't have any interrupt handler for I2C1, so enabling of the I2C1
interrupts will just end up triggering a panic everytime the interrupt
fires.
By the way, I2C1 is used as master and all communications happen without
using the I2C interrupt.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=spring
BUG=chrome-os-partner:18499
TEST=On Spring, run EC flashing in a loop from the AP
while true
do
flashrom --fast-verify -p internal:bus=lpc -w ec.bin
flashrom --fast-verify -p internal:bus=lpc -w ec_autest_image.bin
done
and check that we always succeed and have no panic.
Original-Change-Id: I6b071f309218410840707380d296bdf14b10e9f5
Reviewed-on: https://gerrit.chromium.org/gerrit/47749
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 8b3262d644003b3c9727998dc8d4b0c749450aef)
Change-Id: Ie2fc30e5661e7eade024e6893eaf16427f94cac2
Reviewed-on: https://gerrit.chromium.org/gerrit/49192
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
The power button code is platform-independent. This change splits the
code out of the LM4 switch.c module so that a subseqent change to
STM32 platforms can start using it.
BUG=chrome-os-partner:18945
BRANCH=none
TEST=manual
1. Power+refresh+esc goes to recovery mode,
2. Press power button at recovery screen turns off.
3. With system off, power button turns system on.
4. Press power button for a second; screen locks.
5. Press power button while typing; blocks keystrokes while it's pressed.
6. Hold power button down for 8 sec; system forced to shutdown.
7. From EC console, with system on:
hostevent clear
hostevent -> event 0x04 is clear
press power button
hostevent -> event 0x04 is set
8. From EC console, with system off:
powerbtn -> system turns on
powerbtn 5000 -> system turns off, just like power button was held for 5 sec
Change-Id: If2a9b02514a201e1d03c857d128e2ccab51a16ef
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49217
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
These should be specific to the lm4's lpc.c, not the board.
BUG=chrome-os-partner:18343
TEST=build all, run link
BRANCH=none
Change-Id: Ie02bbd3cf90f09035d302f5dcaad4d33f4ef9e7c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49101
CONFIG_ macros should be set directly. Expanding the task names in the same
way made it difficult to tell what was a configuration choice and what was
due to changes in ec.tasklist
BUG=chrome-os-partner:18343
TEST=build all, run link
BRANCH=none
Change-Id: Ib82e34f974238ee2dd216f33b701b6f4c6a4f1f1
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49098
Reviewed-by: Randall Spangler <rspangler@chromium.org>
UART0 is the EC console, and it's consistent.
UART1 is the AP console that we export via servo. It was connected to a
different set of GPIOS on the BDS.
BUG=chrome-os-partner:18343
TEST=build link, bds
BRANCH=none
Change-Id: Ib4c10fd4d2b7a8ffb4e41e216528d4760ba50de3
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48975
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Some experimental boards may want to build without a battery charging task
to make bringup easier.
BUG=chrome-os-partner:18343
TEST=build all boards
BRANCH=none
Change-Id: I4269fea4046325241ad7720ec3457b0534aadda3
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48974
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This is now consistent with other boards.
No functional changes, just renaming,
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build link, bds
Change-Id: Ifd7c1ec608ab61f5f66800e91803ffafe1d944b6
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48804
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Pit uses GPIO PA2=TIM2_CH3 instead of Snow's PB3=TIM2_CH2. Other than
that, the timer setup is identical (STM32F and STM32L are compatible
in this respect, anyway).
BUG=chrome-os-partner:18657
BRANCH=none
TEST=build snow, pit; no pit boards to test on yet
Change-Id: I8ba68f99641038e12c9a9c9dd29e3b64410a5eef
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48403
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This is a struct representation of the STM32 timer registers, so
belongs in registers.h instead of the platform-independent hwtimer.h.
Note that there are other problems with the use of this struct. It
should be volatile, and if it's a win vs. the macros we should replace
ALL macro'd timer register accesses with the struct instead of just
those in hwtimer.c (that is, we shouldn't do things both ways). I'll
address those in a subsequent CL after testing which way generates the
most compact code.
No functional changes, just moving the struct definition.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: If29d008fb38b9cc847b69eda1ee7c05e67f6e5e7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48415
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This is left over from when we had a pair of macros for each GPIO
register, one which concatenated its base address name and one which
took a base address. Only the latter has survived, but its naming is
longer than it needs to be and isn't consistent with other register
banks (USART, TIM, etc.).
No code changes, just renaming macros.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: I15a282fd01db2a25219970e28ce551d8dc80193f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48226
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This merges flash_overwrite and flash_rw_erase to a single test binary.
BUG=chrome-os-partner:18598
TEST=Run on Spring
BRANCH=None
Change-Id: I1da7577cb5dc196178930dda3a07bb942d959866
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48090
Reviewed-by: Randall Spangler <rspangler@chromium.org>
gpio_set_level() now allows setting the pin level if GPIO_LOW or
GPIO_HIGH is specified. Previously, stm32 platforms did this even
though the definition of gpio_set_level() said it wouldn't work.
Fixed gpio_set_level() not setting level after warm reboot on stm32
because it was checking the GPIO_DEFAULT flag in the wrong place.
Fixed LM4 still mucking with alternate function settings and levels
even if GPIO_DEFAULT was specified.
And checked gpio_list[] and all of the calls to gpio_set_flags() to
make sure everything still behaves the same way it did before (or
better, in the case of actual bugs).
BUG=chrome-os-partner:18718
BRANCH=none
TEST=build all platforms; boot spring and link
Change-Id: I4b84815f76060252df235ff9a37da52c54a8eac5
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48058
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Now pingpong and mutex tests compile. Still need some more work to
handle the i8042-specific KEYPROTO task for keyboard tests.
BUG=chrome-os-partner:18598
TEST=Build tests for link
BRANCH=None
Change-Id: I9ee35d4edb811f17b9a81beb799484a07c0bef14
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47981
All accesses use the _OFF variants. No need to have 2 ways of doing
the same thing.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: I914e6dd9027bcf2268e33ae2e8cfb41093b0b05d
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48032
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
So there's no need to check for BOARD_daisy there
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: I518e4a091d279fc6b23d1c9448362c3b315a6905
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47894
gpio_set_alternate_function() used 0 to mean "normal GPIO function".
But on chips like STM32L, alternate function 0 is actually a function
on some pins. So change "normal GPIO function" to -1.
Also add support for this on STM32L.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build and boot link and daisy
Change-Id: I9cdd9ad91a315b616e373a0dc9a50545cf9d20fa
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47903
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Its implementation is the same on all platforms.
No functional changes, just renaming/moving.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: I78741c6587ea61e7ac8edae5a509502b7ab5078b
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47898
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Nothing has used this since link EVT, so it's just dead code at this point.
BUG=chrome-os-partner:13213
BRANCH=none
TEST=manual
- Update ectool but leave old firmware
- ectool version -> works
- ectool flashread 0 0x10000 foo -> puts the first 64KB of EC flash into foo
- Update firmware
- ectool version -> works
- ectool flashread 0 0x10000 foo -> puts the first 64KB of EC flash into foo
- power+esc+refresh -> recovery mode
Change-Id: Ib25a705bcd8280d5295c8e7890969d796542b6c9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47866
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
And use them for LM4 as well as STM32. Consistency is good.
No functional changes, just moving/renaming code.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: I029a21fadb50726500255219dc38615874a369e7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47700
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Much of the board init duplicated stuff already done in gpio init, so remove it.
Powering the SPI module should be done in spi.c, not board.c.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms; boot EC on daisy
Change-Id: I9a99eeeb971ebbf7de5b9c0548153684fbb7fff6
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47469
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
And remove the daisy power button LED task for now. Since daisy
didn't have a board.c implementation (or a power button LED), its
power LED task did nothing.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build daisy, snow, spring
Change-Id: I1eb3d0bd038d88685e7caad087eb1a1d1495ef9a
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47442
Reviewed-by: Vic Yang <victoryang@chromium.org>
1) Check vs. number of allowable deferred function calls is made at
link time.
2) Added a check for whether hook_call_deferred() has been made after
the start of calculating the time when the hook task should wake. If
it has, go back and recalculate the wake time. This works around a
race condition.
BUG=chrome-os-partner:18473
BRANCH=none
TEST=add a bunch of deferrable functions and recompile; generates a link error
Change-Id: Ie833e2a699c47b6702957ed67bf7d3925f2df099
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47266
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
There's no need for it to be initalized in board_init(); it just needs
to be done before ADC / I2C / SPI initialize.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=boot spring; verify EC communication and 'adc' console command still work
Change-Id: I6039848fe031222d5ca59b459adfe18fc3e8ef08
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47182
Reviewed-by: Vic Yang <victoryang@chromium.org>
