Move the existing fingerprint host command in the driver and
add more of them to prepare the new fingerprint architecture.
The commands are mostly stubbed for now.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
CQ-DEPEND=*364728
BRANCH=none
BUG=b:35648259
TEST=make BOARD=eve_fp (with and without a private repository)
do a fingerprint image capture with 'fptest'.
Change-Id: Ie17a5fde2d6470c6272e8059bddc845cea07aff2
Reviewed-on: https://chromium-review.googlesource.com/491071
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
There's leakage through EC_INT when in S3 to the APs P3300_A rail.
Changing the GPIO config to be an input all EC_INT and all the SPI slave
pins during S3 removes the leakage.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=none
BUG=b:35648259
TEST=on Eve, run int_test before & after suspend/resume successfully.
Change-Id: I68e286c4770831544bea0d58ffa98185fd7ba788
Reviewed-on: https://chromium-review.googlesource.com/469527
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Enable properly the SPI slave command interface to drive the FP MCU from
the main CPU using the EC SPI protocol V3.
Fix the SPI slave driver on STM32L4 along the way:
- the STM32L4 family has the same FIFOs as STM32F0
- on STM32L4, we need to map the DMA requests
- set explicitly the data size (rather than setting an invalid value
which defaults to 8-bit).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:36025702
TEST=On Eve, use the kernel cros_ec_spi driver to communicate with the
FPMCU using the Cros EC SPI protocol V3.
Change-Id: Ib641c141808aa60b3a74611319e18e7a6c3736f0
Reviewed-on: https://chromium-review.googlesource.com/452373
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Add the option to use the PLL connected the 16Mhz HSI oscillator.
Fix the system timer pre-scaling when changing frequency:
- we need to generate an update event immediately as on a 32-bit timer it
might take a very long time before going an actual update event.
- we need to ensure that the OS timestamp is monotonic and sensible
across the frequency jump.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:62893
TEST=manual, on STM32L4 console, do several gettime and compare against
wall time, switch to 80Mhz with 'clock pll', verify again gettime
against wall clock.
Change-Id: Ibddbd46173b7594d16fb07e4b57660a50c636568
Reviewed-on: https://chromium-review.googlesource.com/445776
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
