This feature is inconsistent. Not all boards have such a symlink
(for a obvious reason).
This feature is fragile. It's most likely not tested and going to be
broken if not already. Developers won't like it if they have to test
two different ways to build boards before submitting patches.
This feature is not necessary. If you build EC in the standard way
(e.g. make BOARD=samus), these symlinks are not needed.
This feature is wasteful. Extra disk spaces are used and extra lines
are added to Makefile (increasing code complexity slightly).
BUG=chromium:626776
BRANCH=none
TEST=make buildall
Change-Id: Id5444284d773cb0e9225f39abd877441b8f61440
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/359321
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The scheme to disable PD communication in locked RO needs to be
implemented on other platforms, so move it to common code, behind
CONFIG_USB_PD_COMM_LOCKED.
BUG=chrome-os-partner:52157
BRANCH=glados
TEST=Manual on chell. Lock system and boot to recovery, then verify PD
communication is functional. Enable CONFIG_USB_PD_COMM_LOCKED and verify
PD communication isn't functional under the same test conditions.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I8d1f24c0b60cf1c54e329af003b7083ee55ffc40
Reviewed-on: https://chromium-review.googlesource.com/338064
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
With commit e9883124ff, a GPIO_INT macro was added. That change
also required that all instances of GPIO_INT in a board's
gpio.inc file come before any GPIO macros, or the interrupt
handler wouldn't work properly.
This CL just adds a warning comment about requirement to all
gpio.inc files.
BUG=chromium:471331
BRANCH=none
TEST=make buildall, test image on Cr50
This is a change to comments only. There is no new behavior to
verify, although I did run try out one new image just to be sure
nothing stupid happened.
Change-Id: I83f7819929a53bce3a8bae04d15b3ee3bda11738
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/329334
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
stm32f03x and stm32f070 officially do not support an HSI48 clock, so
configure our 48MHz clock using HSI8 and PLL.
BUG=chromium:568717
BRANCH=None
TEST=Verify snoball 1us timer is accurate and we can execute
approximately 48 million NOPs in a second.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ice74de98f18908e53e94f2d95a2ec3cae53e2347
Reviewed-on: https://chromium-review.googlesource.com/317459
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If multiple TCPCs are present on a system then we may have multiple
alert signals, each of which alerts us to the status of a different
TCPC. Make boards with external non cros-ec TCPCs define
tcpc_get_alert_status, which returns alert status based upon any alert
GPIOs present, and then service only ports which are alerting.
BUG=chromium:551683,chrome-os-partner:47851
TEST=Verify snoball PDCMD task sleeps appropriately when no devices are
inserted, and verify ports go to PD_DISCOVERY state when we attach
samus. Also verify that glados / glados_pd can still negotiate PD.
BRANCH=None
Change-Id: Iae6c4e1ef4d6685cb5bf7feef713505925a07c8c
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/313209
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This regulator must be enabled in order to power snoball through the
VBUS path.
BUG=chrome-os-partner:47851
BRANCH=None
TEST=Boot snoball with 12V supply on VBUS, verify that EC is stable
and not resetting constantly.
Change-Id: Id1b79b69f641e0c80160b161fe177aeb9c3de733
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/313811
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Snoball uses DMA2 + DMA3 for UART1 debug console. No changes are needed
to STM32_SYSCFG_CFGR1 since this is the register default config.
BUG=chrome-os-partner:47851
BRANCH=None
TEST=Boot snoball, verify EC console works in both directions.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Id984b63f8c0c2d5c042265fd86b3d0c71fd68e6f
Reviewed-on: https://chromium-review.googlesource.com/313168
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
TIM14 can't be used in our existing master / slave system clock config
due to lacking master mode control / TRGO.
BUG=chrome-os-partner:47851
TEST=Manual on snobal. Verify that timer interrupts function, HOOK_SECOND
hooks are called and watchdog doesn't fire.
BRANCH=None
Change-Id: I659b3cc46cf350fc58d88853fcc3d436b5f37d52
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/313189
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
