Tristage all columns as soon as possible right after the power button is
pressed. This can avoid the silego chip to reset the EC.
Resume the interrupt mode after power button is released so that the
deasserted columns doesn't trigger EC reset.
Also change some function names for export.
BUG=chrome-os-partner:7486
TEST=
press g first, then power button. repeat many times. system is not rebooted.
press power button first, then g. repeat many times. system is not rebooted.
ESC+power is still reseting system.
The long press power button still shutdowns system.
Change-Id: Ie5dec20ec3d3c4ffbd4acf5a4dd7f63eec38af56
The problem comes from the different assumption of interrupt mode in EC and
the PCH. The PCH assumes IRQ1 is edge-triggered and triggered at a rising edge.
However, the auto-IRQ functino of EC is level-triggered and uses low-active to
assert an IRQ. This makes the deadlock so that the kernel never gets an
interrupt until a byte is manually pulled from host.
So, the solution is manually firing an IRQ_1 to host after EC puts a byte to
port 0x60. Note that the auto IRQ needs to be disabled in order to avoid
the interference with manual IRQ generation.
This CL also moves chip specific code to lm4/lpc.c and handle some minor
keyboard commands.
BUG=none
TEST=on hacked baord.
Change-Id: Ib57f5a4d749cb019e4c3c00da110054c4f335c7b
