Add a nested interrupt test to eCTS. Higher priority IRQ is fired,
followed by lower priority IRQ. Handlers should be executed
sequentially.
P1 *-----*
/ \
P2 / *-----*
/ \
task_cts ----* *----
B C A D
BUG=chromium:653195
BRANCH=none
TEST=cts.py -m interrupt; make buildall
Change-Id: Ia9f1bf4205cefe8bdc11cc0aa3ad2057359b73ef
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/409611
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add a nested interrupt test to eCTS. Lower priority IRQ is fired,
followed by higher priority IRQ. Handler executions should be nested.
P1 *-----*
/ \
P2 *----* *----*
/ \
task_cts ----* *----
A B C D
BUG=chromium:653195
BRANCH=none
TEST=cts.py -m gpio, interrupt, timer; make buildall
Change-Id: I34dc7b4e819051b9070a11e69d13d6be704f2e5f
Reviewed-on: https://chromium-review.googlesource.com/408797
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Interrupt test checks whether DUT can be interrupted by an interrupt
and an interrupt handler can be invoked as expected.
Note the previous interrupt test ported from test/interrupt.c runs in
an emulated environment on the host, thus does not test the real
interrupt capability of the chip.
BUG=chromium:653195
BRANCH=none
TEST=Run cts.py -m interrupt
Change-Id: I21cecff07594f048633d1c1b699fb3a1876379e0
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363943
Reviewed-by: Randall Spangler <rspangler@chromium.org>
It's imported from test/interrupt.c and adjusted to CTS.
BUG=chromium:624520
BRANCH=none
TEST=make buildall. Test passed on stm32l476-geval and nucleo-f072rb.
Change-Id: Ie948d284cebad60d97aab1512bb9e3af8838004e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360660
Reviewed-by: Chris Chen <twothreecc@google.com>
