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https://github.com/Telecominfraproject/OpenCellular.git
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154 lines
3.5 KiB
Plaintext
Executable File
154 lines
3.5 KiB
Plaintext
Executable File
# pxlba generated file
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# pxlBA.txt : Extract file used to extract properties for
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# back annotation using packagerxl. Refer to Allegro extract
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# documentation for more details on the syntax of this file
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# and the Extract program.
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# The lines starting with # are comments.
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# The default version of this file extracts the minimum number
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# of properties necessary to ba changes to packaging.
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# To extract additional properties the user must remove the
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# comment character '#' from the appropriate lines. Or
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# add a line with the property name to the appropriate section.
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# a2pxl looks for this file in the current working directory.
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# If it is not found there, it looks for it
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# in the hierarchy in the following location:
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# <installation dir>/tools/pcb/text/views
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# Connection view. File: pinView.dat
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#
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LOGICAL_PIN
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# These properties must not be removed, moved or modified.
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# vvvvvvvvvvvvvvvvvvv
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NET_NAME
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REFDES
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PIN_NUMBER
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FUNC_LOGICAL_PATH
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COMP_DEVICE_TYPE
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FUNC_SCH_SIZE
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FUNC_HAS_FIXED_SIZE
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FUNC_DES
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# ^^^^^^^^^^^^^^^^^^^
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# Any other PIN properties to be back annotated show up here.
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PIN_NET_SHORT
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PIN_NO_SWAP_PIN
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PIN_NO_PIN_ESCAPE
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PIN_PIN_ESCAPE
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PIN_PIN_SIGNAL_MODEL
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PIN_NO_DRC
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PIN_NO_SHAPE_CONNECT
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END
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# Function properties view. File: funcView.dat
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# In order to backannotate function properties you must
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# include FUNC_LOGICAL_PATH.
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#
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FUNCTION
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FUNC_LOGICAL_PATH
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COMP_DEVICE_TYPE
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REFDES
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FUNC_PRIM_FILE
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COMP_PARENT_PPT
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COMP_PARENT_PPT_PART
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COMP_PARENT_PART_TYPE
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FUNC_SCH_SIZE
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FUNC_HAS_FIXED_SIZE
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FUNC_DES
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FUNC_GROUP
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FUNC_ROOM
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FUNC_CDS_FSP_UID
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FUNC_NO_SWAP_PIN
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FUNC_HARD_LOCATION
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FUNC_NO_SWAP_GATE_EXT
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FUNC_CDS_FSP_MAPPED_CELL
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FUNC_CDS_FSP_FPGA_SYMBOL
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FUNC_CDS_FSP_TERM_TYPE
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FUNC_CDS_FSP_TERM_NAME
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FUNC_ROOM
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FUNC_GROUP
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FUNC_CDS_FSP_TERM_INDEX
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FUNC_CDS_FSP_INSTANCE_ID
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FUNC_NO_SWAP_GATE
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FUNC_CDS_FSP_IS_FPGA
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END
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# Component properties view. File: compView.dat
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# In order to backannotate component properties you must
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# include REFDES
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#
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COMPONENT
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REFDES
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COMP_VOLTAGE
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COMP_ROOM
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COMP_GROUP
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COMP_SIGNAL_MODEL
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COMP_NO_XNET_CONNECTION
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# The following two properties are needed to feedback ppt
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# part selections done in Allegro.
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# You may comment them out if you do not use this functionality.
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COMP_PARENT_PPT
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COMP_PARENT_PPT_PART
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COMP_REUSE_ID
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COMP_REUSE_NAME
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COMP_REUSE_INSTANCE
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END
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#
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# Signal properties view. File: netView.dat
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# In order to backannotate signal properties you must
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# include NET_NAME
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#
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NET
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NET_NAME
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NET_LOGICAL_PATH
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NET_CDS_FSP_UID
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NET_SHIELD_NET
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NET_RELATIVE_PROPAGATION_DELAY
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NET_NO_PIN_ESCAPE
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NET_NET_SHORT
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NET_VOLTAGE_LAYER
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NET_VOLTAGE
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NET_RATSNEST_SCHEDULE
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NET_CLOCK_NET
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NET_NET_PHYSICAL_TYPE
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NET_MAX_FINAL_SETTLE
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NET_NO_TEST
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NET_MAX_EXPOSED_LENGTH
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NET_ELECTRICAL_CONSTRAINT_SET
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NET_CDS_FSP_BUS_INDEX
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NET_STUB_LENGTH
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NET_SHIELD_TYPE
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NET_NO_RAT
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NET_PROPAGATION_DELAY
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NET_NO_RIPUP
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NET_MIN_HOLD
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NET_DIFFERENTIAL_PAIR
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NET_MIN_SETUP
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NET_MIN_NECK_WIDTH
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NET_BUS_NAME
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NET_MIN_NOISE_MARGIN
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NET_MATCHED_DELAY
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NET_ECL
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NET_DIFFP_LENGTH_TOL
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NET_DIFFP_2ND_LENGTH
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NET_NET_GROUP_GRP_NAME
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NET_SUBNET_NAME
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NET_MIN_BOND_LENGTH
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NET_MAX_OVERSHOOT
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NET_TS_ALLOWED
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NET_MAX_VIA_COUNT
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NET_EMC_CRITICAL_NET
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NET_CDS_FSP_NET
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NET_PROBE_NUMBER
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NET_NO_ROUTE
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NET_MIN_LINE_WIDTH
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NET_ECL_TEMP
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NET_NO_GLOSS
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NET_ROUTE_PRIORITY
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NET_NET_SPACING_TYPE
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NET_IMPEDANCE_RULE
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END
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