Shelley Chen 50db9a208e soc/intel/skylake: Set PsysPl3 and Pl4 ...

If given a value for PsysPl3 and/or Pl4, set the
appropriate MSR.

BUG=b:71594855
BRANCH=None
TEST=boot up and check MSRs in OS to make sure values are set as
     expected.  Test on Fizz, which will set these values in
     mainboard.

Change-Id: Idbe04f48079b4fa3302d21acd065f2e4c53dd1ed
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>

2018-02-05 19:22:44 +00:00

..

amd

amd/soc/common: Remove cbmem subregions in heap

2018-02-01 17:20:09 +00:00

broadcom

soc: Add Kconfig for each soc vendor

2017-10-23 17:18:32 +00:00

dmp

DMP Vortex86ex board & chip: Remove - using LATE_CBMEM_INIT

2018-01-15 23:23:17 +00:00

imgtec

soc: Add Kconfig for each soc vendor

2017-10-23 17:18:32 +00:00

intel

soc/intel/skylake: Set PsysPl3 and Pl4

2018-02-05 19:22:44 +00:00

lowrisc

RISC-V boards: Stop using the config string

2017-11-07 12:31:00 +00:00

marvell

soc: Add Kconfig for each soc vendor

2017-10-23 17:18:32 +00:00

mediatek

soc/mediatek/mt8173: Remove cast of NULL* to void *

2017-11-03 16:03:30 +00:00

nvidia

soc: Add Kconfig for each soc vendor

2017-10-23 17:18:32 +00:00

qualcomm

soc: Add Kconfig for each soc vendor

2017-10-23 17:18:32 +00:00

rockchip

rockchip/rk3399: Pass coreboot table pointer to ARM TF

2018-02-02 22:19:26 +00:00

samsung

soc: Add Kconfig for each soc vendor

2017-10-23 17:18:32 +00:00

ucb

riscv: Remove config string support

2017-12-02 05:25:00 +00:00