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This CL factors out the SPI flash driver to be a STM32-specific SPI master driver and a common SPI flash driver. BUG=None TEST=Verify on Fruitpie BRANCH=None Change-Id: I9cca918299bc57a6532c85c4452e73f04550a424 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/206582 Reviewed-by: Dmitry Torokhov <dtor@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Daming Chen <ddchen@chromium.org> Tested-by: Daming Chen <ddchen@chromium.org>
188 lines
5.0 KiB
C
188 lines
5.0 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* SPI flash interface for Chrome EC */
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#ifndef __CROS_EC_SPI_FLASH_H
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#define __CROS_EC_SPI_FLASH_H
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/* Obtain SPI flash size from JEDEC size */
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#define SPI_FLASH_SIZE(x) (1 << (x))
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/* SPI flash instructions */
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#define SPI_FLASH_WRITE_ENABLE 0x06
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#define SPI_FLASH_WRITE_DISABLE 0x04
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#define SPI_FLASH_READ_SR1 0x05
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#define SPI_FLASH_READ_SR2 0x35
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#define SPI_FLASH_WRITE_SR 0x01
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#define SPI_FLASH_ERASE_4KB 0x20
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#define SPI_FLASH_ERASE_32KB 0x52
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#define SPI_FLASH_ERASE_64KB 0xD8
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#define SPI_FLASH_ERASE_CHIP 0xC7
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#define SPI_FLASH_READ 0x03
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#define SPI_FLASH_PAGE_PRGRM 0x02
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#define SPI_FLASH_REL_PWRDWN 0xAB
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#define SPI_FLASH_MFR_DEV_ID 0x90
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#define SPI_FLASH_JEDEC_ID 0x9F
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#define SPI_FLASH_UNIQUE_ID 0x4B
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#define SPI_FLASH_SFDP 0x44
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#define SPI_FLASH_ERASE_SEC_REG 0x44
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#define SPI_FLASH_PRGRM_SEC_REG 0x42
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#define SPI_FLASH_READ_SEC_REG 0x48
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#define SPI_FLASH_ENABLE_RESET 0x66
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#define SPI_FLASH_RESET 0x99
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/* Maximum single write size (in bytes) for the W25Q64FV SPI flash */
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#define SPI_FLASH_MAX_WRITE_SIZE 256
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/*
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* Maximum message size (in bytes) for the W25Q64FV SPI flash
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* Instruction (1) + Address (3) + Data (256) = 260
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* Limited by chip maximum input length of write instruction
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*/
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#define SPI_FLASH_MAX_MESSAGE_SIZE (SPI_FLASH_MAX_WRITE_SIZE + 4)
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/* Maximum single read size in bytes. Limited by size of the message buffer */
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#define SPI_FLASH_MAX_READ_SIZE (SPI_FLASH_MAX_MESSAGE_SIZE - 4)
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/* Status register write protect structure */
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enum spi_flash_wp {
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SPI_WP_NONE,
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SPI_WP_HARDWARE,
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SPI_WP_POWER_CYCLE,
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SPI_WP_PERMANENT,
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};
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/**
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* Waits for the chip to finish the current operation. Must be called
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* after erase/erite operations to ensure successive commands are executed.
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*
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* @return EC_SUCCESS, or non-zero if any error.
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*/
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int spi_flash_wait(void);
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/**
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* Returns the contents of SPI flash status register 1
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*
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* @return register contents
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*/
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uint8_t spi_flash_get_status1(void);
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/**
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* Returns the contents of SPI flash status register 2
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*
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* @return register contents
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*/
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uint8_t spi_flash_get_status2(void);
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/**
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* Sets the SPI flash status registers (non-volatile bits only)
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* Pass reg2 == -1 to only set reg1.
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*
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* @param reg1 Status register 1
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* @param reg2 Status register 2 (optional)
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*
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* @return EC_SUCCESS, or non-zero if any error.
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*/
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int spi_flash_set_status(int reg1, int reg2);
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/**
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* Returns the content of SPI flash
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*
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* @param buf Buffer to write flash contents
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* @param offset Flash offset to start reading from
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* @param bytes Number of bytes to read. Limited by receive buffer to 256.
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*
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* @return EC_SUCCESS, or non-zero if any error.
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*/
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int spi_flash_read(uint8_t *buf, unsigned int offset, unsigned int bytes);
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/**
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* Erase SPI flash.
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*
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* @param offset Flash offset to start erasing
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* @param bytes Number of bytes to erase
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*
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* @return EC_SUCCESS, or non-zero if any error.
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*/
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int spi_flash_erase(unsigned int offset, unsigned int bytes);
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/**
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* Write to SPI flash. Assumes already erased.
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* Limited to SPI_FLASH_MAX_WRITE_SIZE by chip.
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*
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* @param offset Flash offset to write
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* @param bytes Number of bytes to write
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* @param data Data to write to flash
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*
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* @return EC_SUCCESS, or non-zero if any error.
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*/
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int spi_flash_write(unsigned int offset, unsigned int bytes,
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const uint8_t const *data);
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/**
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* Returns the SPI flash manufacturer ID and device ID [8:0]
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*
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* @return flash manufacturer + device ID
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*/
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uint16_t spi_flash_get_id(void);
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/**
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* Returns the SPI flash JEDEC ID (manufacturer ID, memory type, and capacity)
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*
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* @return flash JEDEC ID
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*/
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uint32_t spi_flash_get_jedec_id(void);
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/**
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* Returns the SPI flash unique ID (serial)
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*
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* @return flash unique ID
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*/
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uint64_t spi_flash_get_unique_id(void);
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/**
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* Check for SPI flash status register write protection.
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* Note that this does not check the hardware WP pin as we might not be
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* able to read the WP pin status.
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*
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* @param wp Status register write protection mode
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*
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* @return EC_SUCCESS for no protection, or non-zero if error.
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*/
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int spi_flash_check_wp(void);
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/**
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* Set SPI flash status register write protection
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*
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* @param wp Status register write protection mode
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*
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* @return EC_SUCCESS for no protection, or non-zero if error.
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*/
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int spi_flash_set_wp(enum spi_flash_wp);
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/**
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* Check for SPI flash block write protection
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*
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* @param offset Flash block offset to check
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* @param bytes Flash block length to check
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*
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* @return EC_SUCCESS if no protection, or non-zero if error.
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*/
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int spi_flash_check_protect(unsigned int offset, unsigned int bytes);
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/**
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* Set SPI flash block write protection.
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* If offset == bytes == 0, remove protection.
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*
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* @param offset Flash block offset to protect
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* @param bytes Flash block length to protect
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*
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* @return EC_SUCCESS, or non-zero if error.
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*/
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int spi_flash_set_protect(unsigned int offset, unsigned int bytes);
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#endif /* __CROS_EC_SPI_FLASH_H */
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