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https://github.com/Telecominfraproject/OpenCellular.git
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645dad5d3f
Preparatory work to introduce a second SoC : 2/5 The hwtimer.* files implement the driver for the SoC timer block. The timer.* files provides the OS level clock/timer functions. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=on BDS, check 'waitms' and 'gettime' on the EC console. Change-Id: Icbc58d9be59ee268e2d5a94f8b20de0cabcdc91d
92 lines
2.1 KiB
C
92 lines
2.1 KiB
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Hardware timers driver */
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#include <stdint.h>
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#include "board.h"
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#include "hwtimer.h"
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#include "registers.h"
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#include "task.h"
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#define US_PER_SECOND 1000000
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/* Divider to get microsecond for the clock */
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#define CLOCKSOURCE_DIVIDER (CPU_CLOCK/US_PER_SECOND)
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void __hw_clock_event_set(uint32_t deadline)
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{
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/* set the match on the deadline */
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LM4_TIMER_TAMATCHR(6) = 0xffffffff - deadline;
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/* Set the match interrupt */
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LM4_TIMER_IMR(6) |= 0x10;
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}
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uint32_t __hw_clock_event_get(void)
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{
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return 0xffffffff - LM4_TIMER_TAMATCHR(6);
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}
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void __hw_clock_event_clear(void)
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{
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/* Disable the match interrupt */
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LM4_TIMER_IMR(6) &= ~0x10;
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}
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uint32_t __hw_clock_source_read(void)
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{
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return 0xffffffff - LM4_TIMER_TAV(6);
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}
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static void __hw_clock_source_irq(void)
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{
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uint32_t status = LM4_TIMER_RIS(6);
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/* clear interrupt */
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LM4_TIMER_ICR(6) = status;
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/*
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* Find expired timers and set the new timer deadline
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* get from the IRQ status if the free running counter as overflowed
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*/
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process_timers(status & 0x01);
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}
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DECLARE_IRQ(LM4_IRQ_TIMERW0A, __hw_clock_source_irq, 1);
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int __hw_clock_source_init(void)
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{
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volatile uint32_t scratch __attribute__((unused));
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/* Use WTIMER0 (timer 6) configured as a free running counter with 1 us
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* period */
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/* Enable WTIMER0 clock */
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LM4_SYSTEM_RCGCWTIMER |= 1;
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/* wait 3 clock cycles before using the module */
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scratch = LM4_SYSTEM_RCGCWTIMER;
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/* Ensure timer is disabled : TAEN = TBEN = 0 */
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LM4_TIMER_CTL(6) &= ~0x101;
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/* Set overflow interrupt */
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LM4_TIMER_IMR(6) = 0x1;
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/* 32-bit timer mode */
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LM4_TIMER_CFG(6) = 4;
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/* set the prescaler to increment every microsecond */
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LM4_TIMER_TAPR(6) = CLOCKSOURCE_DIVIDER;
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/* Periodic mode, counting down */
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LM4_TIMER_TAMR(6) = 0x22;
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/* use the full 32-bits of the timer */
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LM4_TIMER_TAILR(6) = 0xffffffff;
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/* Starts counting in timer A */
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LM4_TIMER_CTL(6) |= 0x1;
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/* Enable interrupt */
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task_enable_irq(LM4_IRQ_TIMERW0A);
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return LM4_IRQ_TIMERW0A;
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}
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