Nishanth Menon 861ac52a7e uart: 16550: Fix getc ...

tbz check for RDR status is to check for a bit being zero.
Unfortunately, we are using a mask rather than the bit position.

Further as per http://www.ti.com/lit/ds/symlink/pc16550d.pdf (page 17),
LSR register bit 0 is Data ready status (RDR), not bit position 2.

Update the same to match the specification.

Reported-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>

2017-01-10 09:36:44 -06:00

..

uart_16550.h

uart: 16550: Fix getc

2017-01-10 09:36:44 -06:00