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d7b938f857
This patch adds the initial support for ISH chip to enable the EC firmware to boot on Intel Integrated Sensor Hub (ISH). The following are enabled: 1. Inter-Processor Communication (IPC) driver that enables the ISH to communicate with the host Operating system via shared registers. 2. High Precision Event Timer (HPET) driver that provides configurable timers for the FW to use in task scheduling. 3. I2C bus driver for accessing sensors. 4. UART console driver with TX support only. BUG=chrome-os-partner:51851 BRANCH=None TEST=`make buildall -j` Change-Id: I15d4c201b799cfa79bed220ee573b75f5cd7b1f7 Signed-off-by: Jaiber John <jaiber.j.john@intel.com> Signed-off-by: Alex Brill <alexander.brill@intel.com> Signed-off-by: Gomathi Kumar <gomathi.kumar@intel.com> Reviewed-on: https://chromium-review.googlesource.com/336710 Commit-Ready: Raj Mojumder <raj.mojumder@intel.com> Tested-by: Jaiber J John <jaiber.j.john@intel.com> Tested-by: Raj Mojumder <raj.mojumder@intel.com> Reviewed-by: Jaiber J John <jaiber.j.john@intel.com> Reviewed-by: Raj Mojumder <raj.mojumder@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
60 lines
1.9 KiB
C
60 lines
1.9 KiB
C
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CONFIG_FLASH_LAYOUT_H
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#define __CROS_EC_CONFIG_FLASH_LAYOUT_H
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/* Mem-mapped, No external SPI for ISH */
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#undef CONFIG_EXTERNAL_STORAGE
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#define CONFIG_MAPPED_STORAGE
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#undef CONFIG_FLASH_PSTATE
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#undef CONFIG_SPI_FLASH
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#define CONFIG_ISH_BOOT_START 0xFF000000
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/*****************************************************************************/
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/* The following macros are not applicable for ISH, however the build fails if
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* they are not defined. Ideally, there should be an option in EC build to
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* turn off SPI and flash, making these unnecessary.
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*/
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#define CONFIG_MAPPED_STORAGE_BASE 0x0
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#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE - 0x20000)
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#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000
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#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE - 0x40000)
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#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000
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/* Unused for ISH - loader is external to ISH FW */
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#define CONFIG_LOADER_MEM_OFF 0
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#define CONFIG_LOADER_SIZE 0xC00
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/* RO/RW images - not relevant for ISH
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*/
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#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + \
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CONFIG_LOADER_SIZE)
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#define CONFIG_RO_SIZE (97 * 1024)
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#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF
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#define CONFIG_RW_SIZE CONFIG_RO_SIZE
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/*****************************************************************************/
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/* Not relevant for ISH */
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#define CONFIG_BOOT_HEADER_STORAGE_OFF 0
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#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x240
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#define CONFIG_LOADER_STORAGE_OFF (CONFIG_BOOT_HEADER_STORAGE_OFF + \
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CONFIG_BOOT_HEADER_STORAGE_SIZE)
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/* RO image immediately follows the loader image */
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#define CONFIG_RO_STORAGE_OFF (CONFIG_LOADER_STORAGE_OFF + \
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CONFIG_LOADER_SIZE)
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/* RW image starts at the beginning of SPI */
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#define CONFIG_RW_STORAGE_OFF 0
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#endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */
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