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https://github.com/Telecominfraproject/OpenCellular.git
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d7b938f857
This patch adds the initial support for ISH chip to enable the EC firmware to boot on Intel Integrated Sensor Hub (ISH). The following are enabled: 1. Inter-Processor Communication (IPC) driver that enables the ISH to communicate with the host Operating system via shared registers. 2. High Precision Event Timer (HPET) driver that provides configurable timers for the FW to use in task scheduling. 3. I2C bus driver for accessing sensors. 4. UART console driver with TX support only. BUG=chrome-os-partner:51851 BRANCH=None TEST=`make buildall -j` Change-Id: I15d4c201b799cfa79bed220ee573b75f5cd7b1f7 Signed-off-by: Jaiber John <jaiber.j.john@intel.com> Signed-off-by: Alex Brill <alexander.brill@intel.com> Signed-off-by: Gomathi Kumar <gomathi.kumar@intel.com> Reviewed-on: https://chromium-review.googlesource.com/336710 Commit-Ready: Raj Mojumder <raj.mojumder@intel.com> Tested-by: Jaiber J John <jaiber.j.john@intel.com> Tested-by: Raj Mojumder <raj.mojumder@intel.com> Reviewed-by: Jaiber J John <jaiber.j.john@intel.com> Reviewed-by: Raj Mojumder <raj.mojumder@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
97 lines
2.7 KiB
C
97 lines
2.7 KiB
C
/* Copyright (c) 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* IPC module for ISH */
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#ifndef __CROS_EC_IPC_H
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#define __CROS_ECIPC_H
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#define IPC_FAILURE -1
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#define IPC_TIMEOUT -1
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#define UNSET_PIMR 0
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#define SET_PIMR 1
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#define SET_BUSY 1
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#define IPC_PROTOCOL_MNG 3 /* Management protocol */
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#define IPC_PROTOCOL_ECP 4 /* EC protocol */
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#define MNG_TIME_UPDATE 5
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#define EVENT_FLAG_BIT_READ_IPC (1<<0)
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#define EVENT_FLAG_BIT_WRITE_IPC (1<<2)
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#define IPC_PIMR_HOST2ISH_OFFS (0)
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#define IPC_PIMR_HOST2ISH_OFFS (0)
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#define IPC_PIMR_ISH2HOST_CLR_OFFS (11)
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#define IPC_INT_ISH2HOST_CLR_OFFS (0)
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#define IPC_PISR_HOST2ISH_OFFS IPC_PIMR_HOST2ISH_OFFS
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#define IPC_MSG_MAX_SIZE 0x80
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#define IPC_DRBL_BUSY_OFFS (31)
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#define IPC_HEADER_PROTOCOL_OFFSET 10
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#define IPC_HEADER_PROTOCOL_MASK (0x0F)
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#define IPC_HEADER_MNG_CMD_MASK (0x0F)
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#define IPC_HEADER_LENGTH_MASK (0x03FF)
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#define IPC_HEADER_MNG_CMD_OFFSET 16
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#define IPC_HEADER_LENGTH_OFFSET 0
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#define IPC_OOB_MSG_OFFS (30)
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#define IPC_PIMR_HOST2ISH_BIT (1 << IPC_PIMR_HOST2ISH_OFFS)
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#define IPC_PIMR_ISH2HOST_CLR_MASK_BIT (1 << IPC_PIMR_ISH2HOST_CLR_OFFS)
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#define IPC_PIMR_HOST2ISH_BIT (1 << IPC_PIMR_HOST2ISH_OFFS)
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#define IPC_INT_ISH2HOST_CLR_BIT (1 << IPC_INT_ISH2HOST_CLR_OFFS)
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#define IPC_PISR_HOST2ISH_BIT (1 << IPC_PISR_HOST2ISH_OFFS)
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#define IPC_OOB_MSG_BIT (1 << IPC_OOB_MSG_OFFS)
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#define IPC_DRBL_BUSY_BIT (1 << IPC_DRBL_BUSY_OFFS)
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#define IPC_IS_BUSY(drbl_reg) \
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((drbl_reg & IPC_DRBL_BUSY_BIT) == ((uint32_t) IPC_DRBL_BUSY_BIT))
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#define IPC_HEADER_GET_PROTOCOL(drbl_reg) \
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((drbl_reg >> IPC_HEADER_PROTOCOL_OFFSET) & IPC_HEADER_PROTOCOL_MASK)
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#define IPC_HEADER_GET_MNG_CMD(drbl_reg) \
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((drbl_reg >> IPC_HEADER_MNG_CMD_OFFSET) & IPC_HEADER_MNG_CMD_MASK)
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#define IPC_HEADER_GET_LENGTH(drbl_reg) \
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((drbl_reg >> IPC_HEADER_LENGTH_OFFSET) & IPC_HEADER_LENGTH_MASK)
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#define IPC_BUILD_HEADER(length, protocol, busy) \
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((busy << IPC_DRBL_BUSY_OFFS) \
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| (protocol << IPC_HEADER_PROTOCOL_OFFSET) \
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| (length << IPC_HEADER_LENGTH_OFFSET))
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#define IPC_BUILD_MNG_MSG(cmd, length) \
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((1 << IPC_DRBL_BUSY_OFFS)\
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| (IPC_PROTOCOL_MNG << IPC_HEADER_PROTOCOL_OFFSET) \
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| (cmd << IPC_HEADER_MNG_CMD_OFFSET)\
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| (length << IPC_HEADER_LENGTH_OFFSET))
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struct ipc_if_ctx {
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uint32_t in_msg_reg;
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uint32_t out_msg_reg;
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uint32_t in_drbl_reg;
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uint32_t out_drbl_reg;
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uint32_t clr_bit;
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uint8_t irq_in;
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uint8_t irq_clr;
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};
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struct ipc_oob_msg {
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uint32_t address;
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uint32_t length;
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};
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enum pimr_signal_type {
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PIMR_SIGNAL_IN = 0,
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PIMR_SIGNAL_OUT = 1,
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PIMR_SIGNAL_CLR = 2,
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};
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enum {
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IPC_PEER_HOST_ID = 0,
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IPC_PEERS_COUNT,
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};
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#endif /* __CROS_ECIPC_H */
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