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0a6a7be572
Add Microchip MEC17xx family SPI master controllers and flash files. SPI implements public interface wrapper for QMSPI and GPSPI. MEC17xx family uses QMSPI for loading EC firmware. GPSPI is for general use (sensor). BRANCH=none BUG= TEST=Review only. Change-Id: I23001e254dd437caa0917949f4dd2eb903f1adb1 Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
104 lines
3.5 KiB
C
104 lines
3.5 KiB
C
/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CONFIG_FLASH_LAYOUT_H
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#define __CROS_EC_CONFIG_FLASH_LAYOUT_H
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/*
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* mec17xx flash layout:
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* - Non memory-mapped, external SPI.
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* - RW image at the beginning of writable region.
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* - Bootloader at the beginning of protected region, followed by RO image.
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* - Loader + (RO | RW) loaded into program memory.
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*/
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/* Non-memmapped, external SPI */
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#define CONFIG_EXTERNAL_STORAGE
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#undef CONFIG_MAPPED_STORAGE
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#undef CONFIG_FLASH_PSTATE
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#define CONFIG_SPI_FLASH
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/*
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* MEC17xx BootROM uses two 4-byte TAG's at SPI offset 0x0 and 0x04.
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* One valid TAG must be present.
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* TAG's point to a Header which must be located on a 256 byte
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* boundary anywhere in the flash (24-bit addressing).
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* Locate BootROM load Header + LFW + EC_RO at start of second
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* 4KB sector (offset 0x1000).
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* Locate BootROM load Header + EC_RW at start of second half of
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* SPI flash.
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* LFW size is 4KB
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* EC_RO and EC_RW padded sizes from the build are 188KB each.
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* Storage size is 1/2 flash size.
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*/
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#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
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/* Lower 256KB of flash is protected region */
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#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
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/* Writable storage for EC_RW starts at 256KB */
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#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000
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/* Writeable storage is 256KB */
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#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000
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/* Loader resides at the beginning of program memory */
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#define CONFIG_LOADER_MEM_OFF 0
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#define CONFIG_LOADER_SIZE 0x1000
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/* Write protect Loader and RO Image */
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#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
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/*
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* Write protect LFW + EC_RO
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*/
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#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
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/*
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* RO / RW images follow the loader in program memory. Either RO or RW
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* image will be loaded -- both cannot be loaded at the same time.
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*/
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#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + \
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CONFIG_LOADER_SIZE)
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/*
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* MEC1701H Code + Data SRAM size = 256KB
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* Allocate 32KB for data leaving 192KB for Code.
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* The loader is resident in first 4KB of Code SRAM.
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* EC_RO/RW can load 192 - 4 = 188 KB maximum.
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* !!! This size MUST be a multiple of flash erase block size.
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* defined by CONFIG_FLASH_ERASE_SIZE in chip/config_chip.h !!!
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*/
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#define CONFIG_RO_SIZE (188 * 1024)
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#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF
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#define CONFIG_RW_SIZE CONFIG_RO_SIZE
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/*
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* WP region consists of first half of SPI containing TAGs at beginning
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* of SPI flash and header + binary(LFW+EC_RO) at offset 0x1000.
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* Two 4-byte TAG's exist at offset 0 and 4 in the SPI flash device.
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* We only use first TAG pointing to LFW + EC_RO.
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* Header size is 128 bytes. Firmware binary is located immediately
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* after the header.
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* Second half of SPI flash contains:
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* Header(128 bytes) + EC_RW
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*/
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#define CONFIG_BOOT_HEADER_STORAGE_OFF 0x1000
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#define CONFIG_RW_BOOT_HEADER_STORAGE_OFF 0x0
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#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x80
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/* Loader / lfw image immediately follows the boot header on SPI */
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#define CONFIG_LOADER_STORAGE_OFF (CONFIG_BOOT_HEADER_STORAGE_OFF + \
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CONFIG_BOOT_HEADER_STORAGE_SIZE)
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/* RO image immediately follows the loader image */
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#define CONFIG_RO_STORAGE_OFF (CONFIG_LOADER_STORAGE_OFF + \
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CONFIG_LOADER_SIZE)
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/*
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* Header + RW image starts at offset 0 of second half of SPI.
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*/
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#define CONFIG_RW_STORAGE_OFF (CONFIG_RW_BOOT_HEADER_STORAGE_OFF + \
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CONFIG_BOOT_HEADER_STORAGE_SIZE)
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#endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */
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