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c56df0d831
Add Micorchip MEC17xx family files for hardware timers, keyboard scan, host port 80h, UART, and watch dog timer. BRANCH=none BUG= TEST=Review only. Change-Id: Iac8a912af4d29521964f606637041b06fa7238ee Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
122 lines
2.8 KiB
C
122 lines
2.8 KiB
C
/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Hardware timers driver */
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#include "clock.h"
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#include "common.h"
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#include "hooks.h"
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#include "hwtimer.h"
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#include "registers.h"
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#include "task.h"
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#include "timer.h"
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#include "tfdp_chip.h"
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void __hw_clock_event_set(uint32_t deadline)
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{
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MCHP_TMR32_CNT(1) = MCHP_TMR32_CNT(0) -
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(0xffffffff - deadline);
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MCHP_TMR32_CTL(1) |= (1 << 5);
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}
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uint32_t __hw_clock_event_get(void)
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{
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return MCHP_TMR32_CNT(1) - MCHP_TMR32_CNT(0) + 0xffffffff;
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}
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void __hw_clock_event_clear(void)
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{
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MCHP_TMR32_CTL(1) &= ~(1 << 5);
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}
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uint32_t __hw_clock_source_read(void)
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{
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return 0xffffffff - MCHP_TMR32_CNT(0);
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}
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void __hw_clock_source_set(uint32_t ts)
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{
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MCHP_TMR32_CTL(0) &= ~(1 << 5);
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MCHP_TMR32_CNT(0) = 0xffffffff - ts;
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MCHP_TMR32_CTL(0) |= (1 << 5);
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}
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/*
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* Always clear both timer and aggregator status
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*/
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static void __hw_clock_source_irq(int timer_id)
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{
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MCHP_TMR32_STS(timer_id & 0x01) |= 1;
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MCHP_INT_SOURCE(MCHP_TMR32_GIRQ) =
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MCHP_TMR32_GIRQ_BIT(timer_id & 0x01);
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/* If IRQ is from timer 0, 32-bit timer overflowed */
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process_timers(timer_id == 0);
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}
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void __hw_clock_source_irq_0(void) { __hw_clock_source_irq(0); }
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DECLARE_IRQ(MCHP_IRQ_TIMER32_0, __hw_clock_source_irq_0, 1);
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void __hw_clock_source_irq_1(void) { __hw_clock_source_irq(1); }
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DECLARE_IRQ(MCHP_IRQ_TIMER32_1, __hw_clock_source_irq_1, 1);
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static void configure_timer(int timer_id)
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{
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uint32_t val;
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/* Ensure timer is not running */
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MCHP_TMR32_CTL(timer_id) &= ~(1 << 5);
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/* Enable timer */
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MCHP_TMR32_CTL(timer_id) |= (1 << 0);
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val = MCHP_TMR32_CTL(timer_id);
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/* Pre-scale = 48 -> 1MHz -> Period = 1us */
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val = (val & 0xffff) | (47 << 16);
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MCHP_TMR32_CTL(timer_id) = val;
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/* Set preload to use the full 32 bits of the timer */
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MCHP_TMR32_PRE(timer_id) = 0xffffffff;
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/* Enable interrupt */
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MCHP_TMR32_IEN(timer_id) |= 1;
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}
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int __hw_clock_source_init(uint32_t start_t)
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{
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MCHP_PCR_SLP_DIS_DEV_MASK(3, MCHP_PCR_SLP_EN3_BTMR32_0 +
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MCHP_PCR_SLP_EN3_BTMR32_1);
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/*
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* The timer can only fire interrupt when its value reaches zero.
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* Therefore we need two timers:
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* - Timer 0 as free running timer
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* - Timer 1 as event timer
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*/
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configure_timer(0);
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configure_timer(1);
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/* Override the count */
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MCHP_TMR32_CNT(0) = 0xffffffff - start_t;
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/* Auto restart */
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MCHP_TMR32_CTL(0) |= (1 << 3);
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/* Start counting in timer 0 */
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MCHP_TMR32_CTL(0) |= (1 << 5);
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/* Enable interrupt */
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task_enable_irq(MCHP_IRQ_TIMER32_0);
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task_enable_irq(MCHP_IRQ_TIMER32_1);
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MCHP_INT_ENABLE(MCHP_TMR32_GIRQ) = MCHP_TMR32_GIRQ_BIT(0) +
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MCHP_TMR32_GIRQ_BIT(1);
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/*
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* Not needed when using direct mode interrupts
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* MCHP_INT_BLK_EN |= (1 << MCHP_TMR32_GIRQ);
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*/
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return MCHP_IRQ_TIMER32_1;
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}
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