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4123b5861e
In old clock driver, the relationships between each clock sources are
ambiguous. For example, we treat OSC_CLK and FM_CLK as the same but
sometimes they're not on npcx5. (Only one OSC_CLK definition cannot
present the npcx ec's clock tree very well.) This CL added FM_CLK,
CORE_CLK, and APBx_CLK definitions and used macro functions to confine
the limitation of each clock sources in clock_chip.h to make it more
clearly.
We also modified the uart driver and fixed its source clock to 15MHz so
far in this CL. Since npcx7 already supports uart wake-up mechanism, we
removed the functions of switching pins from UART to GPIO by CHIP_FAMILY
definitions for saving code space.
It also includes:
1. Remove useless CHIP_VERSION definition.
2. Move frequency multiplier values M/N for OSC_CLK to clock_chip.h
3. Add clock_get_fm_freq() for the modules rely on it. Ex, peci.
4. Add clock turbo utilities for npcx7 series.
5. Support uart wake-up mechanism for npcx7 series.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found.
Passed clock turbo, sysjump and wake-up from UART signals stress
tests on npcx796f evb.
Change-Id: Id01a8a5d0263f0d2438e6346dfa33bcdef2be56e
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/486821
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
173 lines
4.3 KiB
C
173 lines
4.3 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* NPCX-specific clock module for Chrome EC */
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#ifndef __CROS_EC_CLOCK_CHIP_H
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#define __CROS_EC_CLOCK_CHIP_H
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/*
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* EC clock tree plan: (Default OSC_CLK is 40MHz.)
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*
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* Target OSC_CLK for NPCX7 is 90MHz, FMCLK is 45MHz, CPU and APBs is 15MHz.
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* Target OSC_CLK for NPCX5 is 30MHz, FMCLK is 30MHz, CPU and APBs is 15MHz.
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*/
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#if defined(CHIP_FAMILY_NPCX5)
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/*
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* NPCX5 clock tree: (Please refer Figure 55. for more information.)
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*
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* Suggestion:
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* - OSC_CLK >= 30MHz, FPRED should be 1, else 0.
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* (Keep FMCLK in 30-50 MHz possibly which is tested strictly.)
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*/
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/* Target OSC_CLK freq */
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#define OSC_CLK 30000000
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/* Core clock prescaler */
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#if (OSC_CLK >= 30000000)
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#define FPRED 1 /* CORE_CLK = OSC_CLK(FMCLK)/2 */
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#else
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#define FPRED 0 /* CORE_CLK = OSC_CLK(FMCLK) */
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#endif
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/* Core domain clock */
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#define CORE_CLK (OSC_CLK / (FPRED + 1))
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/* FMUL clock */
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#define FMCLK OSC_CLK
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/* APBs source clock */
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#define APBSRC_CLK CORE_CLK
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/* APB1 clock divider */
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#define APB1DIV 3 /* Default APB1 clock = CORE_CLK/4 */
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/* APB2 clock divider */
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#define APB2DIV 0 /* Let APB2 = CORE_CLK since UART baudrate tolerance */
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#elif defined(CHIP_FAMILY_NPCX7)
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/*
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* NPCX7 clock tree: (Please refer Figure 58. for more information.)
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*
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* Suggestion:
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* - OSC_CLK >= 80MHz, XF_RANGE should be 1, else 0.
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* - CORE_CLK > 66MHz, AHB6DIV should be 1, else 0.
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* - CORE_CLK > 50MHz, FIUDIV should be 1, else 0.
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*/
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/* Target OSC_CLK freq */
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#define OSC_CLK 90000000
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/* Core clock prescaler */
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#define FPRED 5 /* CORE_CLK = OSC_CLK/6 */
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/* Core domain clock */
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#define CORE_CLK (OSC_CLK / (FPRED + 1))
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/* FMUL clock */
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#if (OSC_CLK >= 80000000)
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#define FMCLK (OSC_CLK / 2) /* FMUL clock = OSC_CLK/2 if OSC_CLK >= 80MHz */
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#else
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#define FMCLK OSC_CLK /* FMUL clock = OSC_CLK */
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#endif
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/* AHB6 clock */
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#if (CORE_CLK > 66000000)
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#define AHB6DIV 1 /* AHB6_CLK = CORE_CLK/2 if CORE_CLK > 66MHz */
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#else
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#define AHB6DIV 0 /* AHB6_CLK = CORE_CLK */
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#endif
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/* FIU clock divider */
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#if (CORE_CLK > 50000000)
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#define FIUDIV 1 /* FIU_CLK = CORE_CLK/2 */
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#else
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#define FIUDIV 0 /* FIU_CLK = CORE_CLK */
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#endif
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/* APBs source clock */
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#define APBSRC_CLK OSC_CLK
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/* APB1 clock divider */
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#define APB1DIV 5 /* APB1 clock = OSC_CLK/6 */
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/* APB2 clock divider */
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#define APB2DIV 5 /* APB2 clock = OSC_CLK/6 */
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/* APB3 clock divider */
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#define APB3DIV 5 /* APB3 clock = OSC_CLK/6 */
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#endif
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/* Get APB clock freq */
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#define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV + 1))
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/*
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* Frequency multiplier M/N value definitions according to the requested
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* OSC_CLK (Unit:Hz).
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*/
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#if (OSC_CLK > 80000000)
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#define HFCGN 0x82 /* Set XF_RANGE as 1 if OSC_CLK >= 80MHz */
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#else
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#define HFCGN 0x02
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#endif
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#if (OSC_CLK == 100000000)
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#define HFCGMH 0x0B
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#define HFCGML 0xEC
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#elif (OSC_CLK == 90000000)
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#define HFCGMH 0x0A
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#define HFCGML 0xBA
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#elif (OSC_CLK == 80000000)
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#define HFCGMH 0x09
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#define HFCGML 0x89
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#elif (OSC_CLK == 66000000)
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#define HFCGMH 0x0F
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#define HFCGML 0xBC
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#elif (OSC_CLK == 50000000)
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#define HFCGMH 0x0B
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#define HFCGML 0xEC
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#elif (OSC_CLK == 48000000)
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#define HFCGMH 0x0B
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#define HFCGML 0x72
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#elif (OSC_CLK == 40000000)
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#define HFCGMH 0x09
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#define HFCGML 0x89
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#elif (OSC_CLK == 33000000)
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#define HFCGMH 0x07
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#define HFCGML 0xDE
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#elif (OSC_CLK == 30000000)
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#define HFCGMH 0x07
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#define HFCGML 0x27
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#elif (OSC_CLK == 26000000)
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#define HFCGMH 0x06
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#define HFCGML 0x33
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#else
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#error "Unsupported OSC_CLK Frequency"
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#endif
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#if defined(CHIP_FAMILY_NPCX5)
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#if (OSC_CLK > 50000000)
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#error "Unsupported OSC_CLK on NPCX5 series!"
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#endif
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#elif defined(CHIP_FAMILY_NPCX7)
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#if (OSC_CLK > 100000000)
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#error "Unsupported OSC_CLK on NPCX7 series!"
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#endif
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#endif
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/**
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* Return the current FMUL clock frequency in Hz.
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*/
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int clock_get_fm_freq(void);
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/**
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* Return the current APB1 clock frequency in Hz.
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*/
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int clock_get_apb1_freq(void);
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/**
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* Return the current APB2 clock frequency in Hz.
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*/
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int clock_get_apb2_freq(void);
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/**
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* Return the current APB3 clock frequency in Hz.
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*/
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int clock_get_apb3_freq(void);
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/**
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* Set the CPU clock to maximum freq for better performance.
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*/
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void clock_turbo(void);
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/**
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* Set the CPU clock back to normal freq.
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*/
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void clock_turbo_disable(void);
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#endif /* __CROS_EC_CLOCK_CHIP_H */
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