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a0f25e398e
In this CL, we add the following changes to support the CHIP_VARIANT npcx7m6xb and npcx7m7w: 1. Define the code RAM, data RAM, BBRAM base address/size. 2. Initialize the wov.c file for WoV driver development. (It will be compiled only when CHIP_VARIANT=npcx7m7w in the build.mk and CONFIG_WAKE_ON_VOICE is defined in board.h) 3. Fix the the incorrect offset of PWDWN_CTRL7 register. BRANCH=none BUG=none TEST=No build errors for make buildall. TEST=Change CHIP_VARIANT to npcx7m7w/npcx7m6xb in board/npcx7_evb/build.mk; "BOARD=npcx7_evb make"; Check ec image can be built. Flash the image on EVB; make sure EVB bootup. Change-Id: I87bccb9097f8f0a6c67f96a8d90adf201ae9e773 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/858637 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
73 lines
2.5 KiB
C
73 lines
2.5 KiB
C
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CONFIG_FLASH_LAYOUT_H
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#define __CROS_EC_CONFIG_FLASH_LAYOUT_H
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/*
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* npcx flash layout:
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* - Memory-mapped external SPI.
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* - Image header at the beginning of protected region, followed by RO image.
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* - RW image starts at the second half of flash.
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*/
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/* Memmapped, external SPI */
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#define CONFIG_EXTERNAL_STORAGE
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#define CONFIG_MAPPED_STORAGE
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/* Storage is memory-mapped, but program runs from SRAM */
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#define CONFIG_MAPPED_STORAGE_BASE 0x64000000
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#undef CONFIG_FLASH_PSTATE
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#if defined(CHIP_VARIANT_NPCX5M5G)
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#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
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#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000
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#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x20000
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#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000
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#elif defined(CHIP_VARIANT_NPCX5M6G)
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#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
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#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
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#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000
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#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000
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#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6G) || \
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defined(CHIP_VARIANT_NPCX7M6XB)
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#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
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#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
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#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000
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#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000
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#elif defined(CHIP_VARIANT_NPCX7M7W)
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#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
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#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x80000
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#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x80000
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#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x80000
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#else
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#error "Unsupported chip variant"
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#endif
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/* Header support which is used by booter to copy FW from flash to code ram */
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#define NPCX_RO_HEADER
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#define CONFIG_RO_HDR_MEM_OFF 0x0
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#define CONFIG_RO_HDR_SIZE 0x40
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#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
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#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
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/* RO firmware in program memory - use all of program memory */
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#define CONFIG_RO_MEM_OFF 0
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#define CONFIG_RO_SIZE NPCX_PROGRAM_MEMORY_SIZE
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/*
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* RW firmware in program memory - Identical to RO, only one image loaded at
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* a time.
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*/
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#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF
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#define CONFIG_RW_SIZE CONFIG_RO_SIZE
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/* RO image resides at start of protected region, right after header */
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#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE
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/* RW image resides at start of writable region */
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#define CONFIG_RW_STORAGE_OFF 0
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#endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */
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