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In npcx7, we introduce an enhanced version of Serial Host Interface (SHI) module. This CL adds the support for it. It includes: 1. Increase the size of IBF/OBF from 64 bytes to 128 bytes. 2. Add IBULVL/IBFLVL2 in SHICFG4/SHICFG5 which can configure at which level the IBF pointer reaches to trigger an interrupt to core. The current setting of these two register fields are: IBFLVL - 64 (half full) IBFLVL2 - 8 (the size of host command protocol V3 header) 3. Dedicated CS high/low interrupts. In old SHI module, the way to generate CS high interrupt event is via EOR bit. However, it has a defect that EOR won't be set to 1 when CS is de-asserted if there is no SHI CLK generated. It makes the handling of glitch condition more complicated. In the new SHI module, we introduce the CS high/low interrupts (by enabling the CSnFEN/CSnREEN) to make it easier to handle the glitch. The new SHI module is enabled during SHI initialization when the chip family is npcx7. BRANCH=none BUG=none TEST=No build errors for "make buildall". Test host command communication is ok between npcx7 EVB and a host emulator. Make sure the glitch condition can be detected and handled. Also test the driver on gru, make sure it won't break the operation of old SHI module. Change-Id: If297fd32a0ec2c9e340c60c8f1942868fa978fbc Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/607812 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
25 lines
573 B
C
25 lines
573 B
C
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* NPCX-specific SHI module for Chrome EC */
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#ifndef SHI_CHIP_H_
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#define SHI_CHIP_H_
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#ifdef CONFIG_HOSTCMD_SPS
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/**
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* Called when the NSS level changes, signalling the start of a SHI
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* transaction.
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*
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* @param signal GPIO signal that changed
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*/
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void shi_cs_event(enum gpio_signal signal);
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#ifdef NPCX_SHI_V2
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void shi_cs_gpio_int(enum gpio_signal signal);
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#endif
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#endif
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#endif /* SHI_CHIP_H_ */
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