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b9b5c89c30
Replace the stubs by an actual implementation for ADC and Analog watchdog support on STM32F0xx chips. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=manually read ADC values on STM32F072B discovery. TEST=read all ADC values at once. TEST=Enable watchdog and check it fires when the voltage goes out of range. TEST=read ADC value(s) while watchdog is enabled. TEST=Disable watchdog and check it's actually disabled. Change-Id: Ie6fbd1aa95a3d76394fa47803e8cfc24bf5e4562 Reviewed-on: https://chromium-review.googlesource.com/190710 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
35 lines
884 B
C
35 lines
884 B
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* STM32-specific ADC module for Chrome EC */
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#ifndef __CROS_EC_ADC_CHIP_H
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#define __CROS_EC_ADC_CHIP_H
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/* Data structure to define ADC channels. */
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struct adc_t {
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const char *name;
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int factor_mul;
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int factor_div;
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int shift;
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int channel;
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};
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/*
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* Boards must provide this list of ADC channel definitions. This must match
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* the enum adc_channel list provided by the board. Also, for STM32F0, this
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* must be ordered by AIN ID.
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*/
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extern const struct adc_t adc_channels[];
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/* Minimum and maximum values returned by adc_read_channel(). */
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#define ADC_READ_MIN 0
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#define ADC_READ_MAX 4095
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/* Just plain id mapping for code readability */
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#define STM32_AIN(x) (x)
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#endif /* __CROS_EC_ADC_CHIP_H */
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