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https://github.com/Telecominfraproject/OpenCellular.git
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a625b710c3
Add intial minute-IA (x86) core to to enable the FW to boot on Intel Integrated Sensor Hub (ISH). BUG=chrome-os-partner:51851 BRANCH=None TEST=`make buildall -j` Change-Id: I4dcf841766f216cd00fb1d4214fae19ba5de5603 Signed-off-by: Jaiber John <jaiber.j.john@intel.com> Signed-off-by: Alex Brill <alexander.brill@intel.com> Reviewed-on: https://chromium-review.googlesource.com/336443 Commit-Ready: Raj Mojumder <raj.mojumder@intel.com> Tested-by: Raj Mojumder <raj.mojumder@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
72 lines
1.4 KiB
C
72 lines
1.4 KiB
C
/* Copyright (c) 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "atomic.h"
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inline int bool_compare_and_swap_u32(uint32_t *var, uint32_t old_value,
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uint32_t new_value)
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{
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uint32_t _old_value = old_value;
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__asm__ __volatile__("cmpxchg %1, %2\n"
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: "=a"(old_value)
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: "r"(new_value), "m"(*var), "a" (old_value)
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: "memory");
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return (_old_value == old_value);
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}
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inline void atomic_or_u8(uint8_t *addr, uint8_t bits)
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{
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ATOMIC_OP(or, addr, bits);
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}
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inline void atomic_and_u8(uint8_t *addr, uint8_t bits)
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{
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ATOMIC_OP(and, addr, bits);
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}
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inline void atomic_clear(uint32_t volatile *addr, uint32_t bits)
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{
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ATOMIC_OP(btr, addr, bits >> 1);
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}
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inline void atomic_or(uint32_t volatile *addr, uint32_t bits)
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{
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ATOMIC_OP(orl, addr, bits);
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}
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inline void atomic_add(uint32_t volatile *addr, uint32_t value)
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{
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ATOMIC_OP(addl, addr, value);
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}
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inline void atomic_and(uint32_t volatile *addr, uint32_t value)
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{
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ATOMIC_OP(andl, addr, value);
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}
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inline void atomic_sub(uint32_t volatile *addr, uint32_t value)
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{
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ATOMIC_OP(subl, addr, value);
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}
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inline uint32_t atomic_read_clear(uint32_t volatile *addr)
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{
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int loc = 0;
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if (*addr == 0)
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return 0;
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asm volatile("bsr %1, %0\n"
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"lock; btr %0, %1\n"
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: "=&r" (loc)
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: "m" (*addr)
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: "memory"
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);
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return (1 << loc);
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}
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