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https://github.com/Telecominfraproject/OpenCellular.git
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a625b710c3
Add intial minute-IA (x86) core to to enable the FW to boot on Intel Integrated Sensor Hub (ISH). BUG=chrome-os-partner:51851 BRANCH=None TEST=`make buildall -j` Change-Id: I4dcf841766f216cd00fb1d4214fae19ba5de5603 Signed-off-by: Jaiber John <jaiber.j.john@intel.com> Signed-off-by: Alex Brill <alexander.brill@intel.com> Reviewed-on: https://chromium-review.googlesource.com/336443 Commit-Ready: Raj Mojumder <raj.mojumder@intel.com> Tested-by: Raj Mojumder <raj.mojumder@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
34 lines
1.1 KiB
C
34 lines
1.1 KiB
C
/* Copyright (c) 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Atomic operations for x86 */
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#ifndef __CROS_EC_ATOMIC_H
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#define __CROS_EC_ATOMIC_H
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#include "common.h"
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#include "util.h"
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#define ATOMIC_OP(asm_op, a, v) do { \
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__asm__ __volatile__ ( \
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"lock;" #asm_op " %0, %1\n" \
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: \
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: "r" (v), "m" (*a) \
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: "memory"); \
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} while (0)
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inline int bool_compare_and_swap_u32(uint32_t *var, uint32_t old_value,
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uint32_t new_value);
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inline void atomic_or_u8(uint8_t *var, uint8_t value);
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inline void atomic_and_u8(uint8_t *var, uint8_t value);
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inline void atomic_clear(uint32_t volatile *addr, uint32_t bits);
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inline void atomic_or(uint32_t volatile *addr, uint32_t bits);
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inline void atomic_add(uint32_t volatile *addr, uint32_t value);
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inline void atomic_and(uint32_t volatile *addr, uint32_t value);
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inline void atomic_sub(uint32_t volatile *addr, uint32_t value);
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inline uint32_t atomic_read_clear(uint32_t volatile *addr);
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#endif /* __CROS_EC_ATOMIC_H */
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