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8e4d429172
Grouping the Intel x86 power sequencing common code so that
the future chipset power sequencing implementation can make
use of the existing code.
BUG=chrome-os-partner:59141
BRANCH=none
TEST=make buildall -j
Manually tested on Reef & Chell.
System can boot to OS. S3, S5, hibernate are working.
Change-Id: I29dc208eacb3db47c640d028e9551ab3d8d4288c
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/402272
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
35 lines
1.1 KiB
C
35 lines
1.1 KiB
C
/* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Apollolake chipset power control module for Chrome EC */
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#ifndef __CROS_EC_APOLLOLAKE_H
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#define __CROS_EC_APOLLOLAKE_H
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/*
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* Input state flags.
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* TODO: Normalize the power signal masks from board defines to SoC headers.
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*/
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#define IN_RSMRST_N POWER_SIGNAL_MASK(X86_RSMRST_N)
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#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
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#define IN_SLP_S3_N POWER_SIGNAL_MASK(X86_SLP_S3_N)
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#define IN_SLP_S4_N POWER_SIGNAL_MASK(X86_SLP_S4_N)
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#define IN_SUSPWRDNACK POWER_SIGNAL_MASK(X86_SUSPWRDNACK)
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#define IN_SUS_STAT_N POWER_SIGNAL_MASK(X86_SUS_STAT_N)
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#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_N | \
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IN_SLP_S4_N)
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#define IN_PGOOD_ALL_CORE (IN_RSMRST_N)
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#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
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#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PGOOD_ALL_CORE
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#define CHARGER_INITIALIZED_DELAY_MS 100
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#define CHARGER_INITIALIZED_TRIES 40
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#endif /* __CROS_EC_APOLLOLAKE_H */
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