Files
OpenCellular/power/intel_x86.h
Vijay Hiremath 927b2e754f intel_x86: Handle RSMRST signal in Intel x86 common code
BUG=chrome-os-partner:59141
BRANCH=none
TEST=make buildall -j
     Reef can boot to OS. S3, S5, hibernate are working.

Change-Id: Iddd16cba5f1dc62341dfbc8568b490439b7d593b
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/427018
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-21 10:03:45 -08:00

37 lines
814 B
C

/* Copyright 2016 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Intel X86 chipset power control module for Chrome EC */
#ifndef __CROS_EC_INTEL_X86_H
#define __CROS_EC_INTEL_X86_H
#include "power.h"
/**
* Handle RSMRST signal.
*
* @param state Current chipset state.
*/
void common_intel_x86_handle_rsmrst(enum power_state state);
/**
* Force chipset to G3 state.
*
* @return power_state New chipset state.
*/
enum power_state chipset_force_g3(void);
/**
* Handle power states.
*
* @param state Current chipset state.
* @return power_state New chipset state.
*/
enum power_state common_intel_x86_power_handle_state(enum power_state state);
#endif /* __CROS_EC_INTEL_X86_H */