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afaaba44f1
The utility builds on the extended command protocol recently introduced in the EC and allows to test implementation of various cryptographic primitives available on CR50. This patch brings in the ftdi_spi_tpm.c and mpsse.c from the AOSP trunksd package. mpsse.c has been modified to limit its feature set (no i2c or bigbang support, only SPI0 mode), and ftdit_spi_tpm.c has been modified to properly present binary strings to the Python swig wrapper. The crypro_test.xml file includes descriptions of the tests to perform on the target. Most of its contents other than the first crypto_test element are borrowed from NIST AES test vectors set. See file header for description of the contents format. The actual test command is the tpmtest.py. When started it establishes connection with the device, and then reads test vectors from crypto_test.xml and executes them one at a time. Starting the test program with the -d command line argument enables debug output sent to the console. There are some other programs in ./extras which use the mpsse.c from AOSP, they will have to be modified to use the local copy. BRANCH=none BUG=chrome-os-partner:43025 TEST=ran the following in the directory: $ make # output suppressed $ ./tpmtest.py Starting MPSSE at 800 kHz Connected to device vid:did:rid of 1ae0:0028:00 \New max timeout: 1 s SUCCESS: AES:ECB common SUCCESS: AES:ECB128 1 SUCCESS: AES:ECB192 1 SUCCESS: AES:ECB256 1 SUCCESS: AES:ECB256 2 SUCCESS: AES:CTR128I 1 SUCCESS: AES:CTR256I 1 - temporarily corrupted the contents of the clear_text element of 'AES:ECB common': $ ./tpmtest.py Starting MPSSE at 800 kHz Connected to device vid:did:rid of 1ae0:0028:00 | Out text mismatch in node AES:ECB common, operation 1: In text: 74 68 69 73 20 20 69 73 20 74 68 65 20 74 65 78 74 20 77 68 69 63 68 20 77 69 6c 6c 20 62 65 20 65 6e 63 72 79 70 74 65 64 20 69 66 20 65 76 65 72 79 74 68 69 6e 67 20 69 73 20 67 6f 69 6e 67 20 66 69 6e 65 2e 20 Expected out text: 3d e2 0f f9 ee d9 62 ce f0 8a 17 57 c6 04 86 d0 3d ec 44 72 d8 79 18 87 3f 31 81 6d 66 4c bb 10 da 8d e0 9f 63 67 b3 cc 64 b4 e8 bd 12 b0 a9 c9 09 6d f0 9f a4 e2 ae fb 0d fe 1c 90 6c e2 fe f0 68 8f b5 34 07 76 e2 a9 72 8e dd 7b 8b 52 2b 8b Real out text: f9 50 fe 93 c9 3f cb e5 9e e0 a4 7e 51 1a bb a0 36 2f d1 d6 5f a8 1d 22 5a 1a bb f7 e6 65 89 55 ad e8 f5 8f 1a 20 ff a5 c4 de 76 3e b8 ef cc 8d 9d 94 b8 89 22 1c c9 2a 43 58 c3 8c 75 9f 9f 56 ab 2f 89 1a f6 a0 36 8b 95 23 91 d6 23 47 77 36 Change-Id: I2687ac03236b528e71b92df7cb35606e473ab2c5 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/313443 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
88 lines
1.9 KiB
C
88 lines
1.9 KiB
C
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* Based on Craig Heffner's version of Dec 27 2011, published on
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* https://github.com/devttys0/libmpsse
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*/
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#ifndef __EC_TEST_TPM_TEST_SUPPORT_H
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#define __EC_TEST_TPM_TEST_SUPPORT_H
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#include "mpsse.h"
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#define CMD_SIZE 3
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#define NUM_GPIOL_PINS 4
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#define NUM_GPIO_PINS 12
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#define LOW 0
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#define HIGH 1
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/* Supported MPSSE modes */
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enum modes {
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SPI0 = 1,
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SPI1 = 2,
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SPI2 = 3,
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SPI3 = 4,
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I2C = 5,
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GPIO = 6,
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BITBANG = 7,
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};
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enum low_bits_status {
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STARTED,
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STOPPED
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};
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enum pins {
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SK = 1,
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DO = 2,
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DI = 4,
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CS = 8,
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GPIO0 = 16,
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GPIO1 = 32,
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GPIO2 = 64,
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GPIO3 = 128
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};
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struct mpsse_context {
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char *description;
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struct ftdi_context ftdi;
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enum modes mode;
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enum low_bits_status status;
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int flush_after_read;
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int vid;
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int pid;
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int clock;
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int xsize;
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int open;
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int ftdi_initialized;
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int endianness;
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uint8_t tris;
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uint8_t pstart;
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uint8_t pstop;
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uint8_t pidle;
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uint8_t gpioh;
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uint8_t trish;
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uint8_t bitbang;
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uint8_t tx;
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uint8_t rx;
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uint8_t txrx;
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uint8_t tack;
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uint8_t rack;
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};
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int raw_write(struct mpsse_context *mpsse, unsigned char *buf, int size);
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int raw_read(struct mpsse_context *mpsse, unsigned char *buf, int size);
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void set_timeouts(struct mpsse_context *mpsse, int timeout);
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uint16_t freq2div(uint32_t system_clock, uint32_t freq);
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uint32_t div2freq(uint32_t system_clock, uint16_t div);
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unsigned char *build_block_buffer(struct mpsse_context *mpsse,
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uint8_t cmd,
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unsigned char *data, int size, int *buf_size);
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int set_bits_high(struct mpsse_context *mpsse, int port);
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int set_bits_low(struct mpsse_context *mpsse, int port);
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int gpio_write(struct mpsse_context *mpsse, int pin, int direction);
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int is_valid_context(struct mpsse_context *mpsse);
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#endif /* ! __EC_TEST_TPM_TEST_SUPPORT_H */
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