Icarus Sparry 077e545662 cortex-m: proper handling of input parameters to SVC handler ...

According to section 2.7 of Cortex-M3 Application Note 179: A Cortex-M3
processor can get a "late arriving exception" and this will corrupt the
values of the r0, r1, r2 and r3 registers passed in an svc call.

http://infocenter.arm.com/help/topic/com.arm.doc.dai0179b/AppsNote179.pdf

The fix is to reload the two registers we care about, r0 and r1, from
the stack to ensure the input parameters to SVC handler, desched (r0)
and resched (r1), are valid.

BUG=chrome-os-partner:48499
BRANCH=none
TEST=Used assert to verify resched is a valid TASK ID.

Change-Id: Ie2229472e709febe16eee3c2cd986e3815fda076
Signed-off-by: Icarus Sparry <icarus.w.sparry@intel.com>
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/319849
Commit-Ready: Icarus W Sparry <icarus.w.sparry@intel.com>
Tested-by: Icarus W Sparry <icarus.w.sparry@intel.com>
Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>

2016-01-05 17:26:10 -08:00

..

cortex-m

cortex-m: proper handling of input parameters to SVC handler

2016-01-05 17:26:10 -08:00

cortex-m0

task: Don't discard events on mutex contention

2015-11-30 12:27:58 -08:00

host

task: Don't discard events on mutex contention

2015-11-30 12:27:58 -08:00

nds32

nds32: start_irq_handler() use system stack

2015-12-16 21:49:34 -08:00