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576444aa13
When we lower the runlevel for security purposes, the standard ARM watchdog interrupt is no longer enough to cause a full reboot. We'll manually trigger a system reset instead. For now, it's a soft reset. Should it be hard? BUG=chrome-os-partner:47289 BRANCH=none CQ-DEPEND=CL:310975 TEST=make buildall, manual From the console, run "crash watchdog". After a second or to, the watchdog trace dump appears and the system reboots. Change-Id: I99fcaf19b32728563e3b051755d65267cc11156c Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311298 Reviewed-by: Nagendra Modadugu <ngm@google.com>
119 lines
2.9 KiB
C
119 lines
2.9 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "cpu.h"
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#include "registers.h"
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#include "system.h"
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#include "task.h"
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static void check_reset_cause(void)
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{
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uint32_t reset_source = GR_PMU_RSTSRC;
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uint32_t flags = 0;
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/* Clear the reset source now we have recorded it */
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GR_PMU_CLRRST = 1;
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if (reset_source & (1 << GC_PMU_RSTSRC_POR_LSB))
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flags |= RESET_FLAG_POWER_ON;
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else if (reset_source & (1 << GC_PMU_RSTSRC_EXIT_LSB))
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flags |= RESET_FLAG_WAKE_PIN;
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if (reset_source & (1 << GC_PMU_RSTSRC_WDOG_LSB))
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flags |= RESET_FLAG_WATCHDOG;
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if (reset_source & (1 << GC_PMU_RSTSRC_SOFTWARE_LSB))
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flags |= RESET_FLAG_HARD;
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if (reset_source & (1 << GC_PMU_RSTSRC_SYSRESET_LSB))
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flags |= RESET_FLAG_SOFT;
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if (reset_source & (1 << GC_PMU_RSTSRC_FST_BRNOUT_LSB))
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flags |= RESET_FLAG_BROWNOUT;
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if (reset_source && !flags)
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flags |= RESET_FLAG_OTHER;
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system_set_reset_flags(flags);
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}
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void system_pre_init(void)
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{
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check_reset_cause();
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}
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void system_reset(int flags)
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{
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/* TODO: if (flags & SYSTEM_RESET_PRESERVE_FLAGS), do so. */
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/* Disable interrupts to avoid task swaps during reboot */
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interrupt_disable();
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if (flags & SYSTEM_RESET_HARD) {
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/* Reset the full microcontroller */
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GR_PMU_GLOBAL_RESET = GC_PMU_GLOBAL_RESET_KEY;
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} else {
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/* Soft reset is also fairly hard, and requires
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* permission registers to be reset to their initial
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* state. To accomplish this, first register a wakeup
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* timer and then enter lower power mode. */
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/* Low speed timers continue to run in low power mode. */
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GREG32(TIMELS, TIMER1_CONTROL) = 0x1;
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/* Wait for this long. */
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GREG32(TIMELS, TIMER1_LOAD) = 1;
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/* Setup wake-up on Timer1 firing. */
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GREG32(PMU, EXITPD_MASK) =
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GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_MASK;
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/* All the components to power cycle. */
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GREG32(PMU, LOW_POWER_DIS) =
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GC_PMU_LOW_POWER_DIS_VDDL_MASK |
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GC_PMU_LOW_POWER_DIS_VDDIOF_MASK |
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GC_PMU_LOW_POWER_DIS_VDDXO_MASK |
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GC_PMU_LOW_POWER_DIS_JTR_RC_MASK;
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/* Start low power sequence. */
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REG_WRITE_MLV(GREG32(PMU, LOW_POWER_DIS),
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GC_PMU_LOW_POWER_DIS_START_MASK,
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GC_PMU_LOW_POWER_DIS_START_LSB,
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1);
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}
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/* Wait for reboot; should never return */
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asm("wfi");
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}
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const char *system_get_chip_vendor(void)
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{
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return "g";
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}
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const char *system_get_chip_name(void)
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{
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return "cr50";
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}
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const char *system_get_chip_revision(void)
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{
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int build_date = GR_SWDP_BUILD_DATE;
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int build_time = GR_SWDP_BUILD_TIME;
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if ((build_date != GC_SWDP_BUILD_DATE_DEFAULT) ||
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(build_time != GC_SWDP_BUILD_TIME_DEFAULT))
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return GC_REVISION_STR" BUILD MISMATCH!";
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else
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return GC_REVISION_STR;
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}
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/* TODO(crosbug.com/p/33822): Where can we store stuff persistently? */
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int system_get_vbnvcontext(uint8_t *block)
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{
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return 0;
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}
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int system_set_vbnvcontext(const uint8_t *block)
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{
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return 0;
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}
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