Lin Huang 09f41f8ed6 rockchip: rk3399: dram: set all ddr frequency pll_postdiv values to 0 ...

The phy pll needs to get 2X frequency to the DDR, so set the
pll_postdiv to 0.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>

2017-02-24 20:07:44 +08:00

..

arm

Resolve build errors flagged by GCC 6.2

2017-01-26 13:47:37 +00:00

common

tbbr: Simplify conditional

2017-01-31 10:55:04 +00:00

compat

AArch32: Add essential ARM platform and FVP support

2016-08-10 18:01:38 +01:00

mediatek

Remove use of all deprecated APIs

2017-01-24 10:50:14 +08:00

nvidia/tegra

Use #ifdef for IMAGE_BL* instead of #if

2017-01-24 01:01:21 +09:00

qemu

Use #ifdef for IMAGE_BL* instead of #if

2017-01-24 01:01:21 +09:00

rockchip

rockchip: rk3399: dram: set all ddr frequency pll_postdiv values to 0

2017-02-24 20:07:44 +08:00

xilinx/zynqmp

Move BL_COHERENT_RAM_BASE/END defines to common_def.h

2017-01-18 19:33:41 +09:00