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a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
116 lines
3.1 KiB
C
116 lines
3.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Imagination Technologies
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/cache.h>
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#include <arch/cpu.h>
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#include <console/console.h>
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#include <program_loading.h>
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#include <symbols.h>
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/* cache_op: issues cache operation for specified address */
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#define cache_op(op, addr) \
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({ \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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".set mips32\n\t" \
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"cache %0, %1\n\t" \
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".set mips0\n\t" \
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".set pop\n\t" \
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: \
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: "i" (op), "R" (*(unsigned char *)(addr))); \
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})
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#define MIPS_CONFIG1_DL_SHIFT 10
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#define MIPS_CONFIG1_DL_MASK (0x00000007)
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#define MIPS_CONFIG1_IL_SHIFT 19
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#define MIPS_CONFIG1_IL_MASK (0x00000007)
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#define MIPS_CONFIG2_SL_SHIFT 4
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#define MIPS_CONFIG2_SL_MASK (0x0000000F)
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/*
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* get_cache_line_size:
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* Read config register
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* Isolate instruction cache line size
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* Interpret value as per MIPS manual: 2 << value
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* Return cache line size
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*/
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static int get_cache_line_size(uint8_t type)
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{
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switch (type) {
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case ICACHE:
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return 2 << ((read_c0_config1() >> MIPS_CONFIG1_IL_SHIFT) &
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MIPS_CONFIG1_IL_MASK);
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case DCACHE:
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return 2 << ((read_c0_config1() >> MIPS_CONFIG1_DL_SHIFT) &
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MIPS_CONFIG1_DL_MASK);
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case L2CACHE:
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return 2 << ((read_c0_config2() >> MIPS_CONFIG2_SL_SHIFT) &
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MIPS_CONFIG2_SL_MASK);
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default:
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printk(BIOS_ERR, "%s: Error: unsupported cache type.\n",
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__func__);
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return 0;
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}
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return 0;
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}
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void perform_cache_operation(uintptr_t start, size_t size, uint8_t operation)
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{
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u32 line_size, line_mask;
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uintptr_t end;
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line_size = get_cache_line_size((operation >> CACHE_TYPE_SHIFT) &
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CACHE_TYPE_MASK);
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if (!line_size)
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return;
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line_mask = ~(line_size-1);
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end = (start + (line_size - 1) + size) & line_mask;
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start &= line_mask;
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if ((operation & L2CACHE) == L2CACHE)
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write_c0_l23taglo(0);
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while (start < end) {
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switch (operation) {
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case CACHE_CODE(ICACHE, WB_INVD):
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cache_op(CACHE_CODE(ICACHE, WB_INVD), start);
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break;
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case CACHE_CODE(DCACHE, WB_INVD):
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cache_op(CACHE_CODE(DCACHE, WB_INVD), start);
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break;
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case CACHE_CODE(L2CACHE, WB_INVD):
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cache_op(CACHE_CODE(L2CACHE, WB_INVD), start);
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break;
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default:
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return;
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}
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start += line_size;
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}
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asm("sync");
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}
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void cache_invalidate_all(uintptr_t start, size_t size)
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{
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perform_cache_operation(start, size, CACHE_CODE(ICACHE, WB_INVD));
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perform_cache_operation(start, size, CACHE_CODE(DCACHE, WB_INVD));
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perform_cache_operation(start, size, CACHE_CODE(L2CACHE, WB_INVD));
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}
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void arch_segment_loaded(uintptr_t start, size_t size, int flags)
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{
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cache_invalidate_all(start, size);
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if (flags & SEG_FINAL)
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cache_invalidate_all((uintptr_t)_cbfs_cache, _cbfs_cache_size);
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}
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