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b4d996a5ea
The SCB registers are defined in the ARMv7-M architecture, so they are common to all chips. We will need System Control Register (SCR aka SYSCTRL) to implement power management on stm32. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=make BOARD=link && make BOARD=snow Change-Id: I35c283731306541b3d21398c96fdca89954fe20a Reviewed-on: https://gerrit.chromium.org/gerrit/25392 Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
27 lines
840 B
C
27 lines
840 B
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* Registers map and defintions for Cortex-MLM4x processor
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*/
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#ifndef __CPU_H
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#define __CPU_H
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#include <stdint.h>
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/* Macro to access 32-bit registers */
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#define CPUREG(addr) (*(volatile uint32_t*)(addr))
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/* Nested Vectored Interrupt Controller */
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#define CPU_NVIC_EN(x) CPUREG(0xe000e100 + 4 * (x))
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#define CPU_NVIC_DIS(x) CPUREG(0xe000e180 + 4 * (x))
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#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280 + 4 * (x))
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#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x))
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#define CPU_NVIC_APINT CPUREG(0xe000ed0c)
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#define CPU_NVIC_SWTRIG CPUREG(0xe000ef00)
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#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10)
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#endif /* __CPU_H */
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