mirror of
https://github.com/Telecominfraproject/OpenCellular.git
synced 2026-01-03 21:49:32 +00:00
b2ac77b37b
This is necessary at init-time for verified boot to jump from RO to one of the RW images. It's also used by factory EC update to update one image and then jump to the updated image to finish the update. In this case, the x86 does NOT reboot. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8449 TEST=manual 1) power on x86 and log in 2) sysjump a --> system is in a; x86 has not rebooted 3) sysjump ro --> system is back in RO; x86 has not rebooted 4) reboot -> system is in RO; x86 HAS rebooted Change-Id: I9dbadcf9775e146a0718abfd4ee0758b65350a87
25 lines
789 B
C
25 lines
789 B
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
|
|
* Use of this source code is governed by a BSD-style license that can be
|
|
* found in the LICENSE file.
|
|
*
|
|
* Registers map and defintions for Cortex-MLM4x processor
|
|
*/
|
|
|
|
#ifndef __CPU_H
|
|
#define __CPU_H
|
|
|
|
#include <stdint.h>
|
|
|
|
/* Macro to access 32-bit registers */
|
|
#define CPUREG(addr) (*(volatile uint32_t*)(addr))
|
|
|
|
/* Nested Vectored Interrupt Controller */
|
|
#define CPU_NVIC_EN(x) CPUREG(0xe000e100 + 4 * (x))
|
|
#define CPU_NVIC_DIS(x) CPUREG(0xe000e180 + 4 * (x))
|
|
#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280 + 4 * (x))
|
|
#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x))
|
|
#define CPU_NVIC_APINT CPUREG(0xe000ed0c)
|
|
#define CPU_NVIC_SWTRIG CPUREG(0xe000ef00)
|
|
|
|
#endif /* __CPU_H */
|