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One of the most common hangs during coreboot execution is during ramstage device init steps. Currently there are a set of (somewhat misleading) post codes during this phase which give some indication as to where execution stopped, but it provides no information on what device was actually being initialized at that point. This uses the new CMOS "extra" log banks to store the encoded device path of the device that is about to be touched by coreboot. This way if the system hangs when talking to the device there will be some indication where to investigate next. interrupted boot with reset button and gathered the eventlog after several test runs: 26 | 2013-06-10 10:32:48 | System boot | 120 27 | 2013-06-10 10:32:48 | Last post code in previous boot | 0x75 | Device Initialize 28 | 2013-06-10 10:32:48 | Extra info from previous boot | PCI | 00:16.0 29 | 2013-06-10 10:32:48 | Reset Button 30 | 2013-06-10 10:32:48 | System Reset Change-Id: I6045bd4c384358b8a4e464eb03ccad639283939c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58105 Reviewed-on: http://review.coreboot.org/4230 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
170 lines
3.7 KiB
C
170 lines
3.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2003 Eric Biederman
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#if CONFIG_CMOS_POST
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#include <pc80/mc146818rtc.h>
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#include <smp/spinlock.h>
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#endif
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#if CONFIG_CMOS_POST_EXTRA
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#include <device/device.h>
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#endif
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#include <elog.h>
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/* Write POST information */
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/* someday romcc will be gone. */
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#ifndef __ROMCC__
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/* Some mainboards have very nice features beyond just a simple display.
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* They can override this function.
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*/
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void __attribute__((weak)) mainboard_post(uint8_t value)
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{
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}
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#else
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/* This just keeps the number of #ifs to a minimum */
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#define mainboard_post(x)
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#endif
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#if CONFIG_CMOS_POST
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DECLARE_SPIN_LOCK(cmos_post_lock)
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#if !defined(__PRE_RAM__)
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void cmos_post_log(void)
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{
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u8 code = 0;
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#if CONFIG_CMOS_POST_EXTRA
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u32 extra = 0;
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#endif
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spin_lock(&cmos_post_lock);
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/* Get post code from other bank */
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switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
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case CMOS_POST_BANK_0_MAGIC:
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code = cmos_read(CMOS_POST_BANK_1_OFFSET);
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#if CONFIG_CMOS_POST_EXTRA
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extra = cmos_read32(CMOS_POST_BANK_1_EXTRA);
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#endif
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break;
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case CMOS_POST_BANK_1_MAGIC:
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code = cmos_read(CMOS_POST_BANK_0_OFFSET);
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#if CONFIG_CMOS_POST_EXTRA
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extra = cmos_read32(CMOS_POST_BANK_0_EXTRA);
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#endif
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break;
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}
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spin_unlock(&cmos_post_lock);
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/* Check last post code in previous boot against normal list */
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switch (code) {
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case POST_OS_BOOT:
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case POST_OS_RESUME:
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case POST_ENTER_ELF_BOOT:
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case 0:
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break;
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default:
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printk(BIOS_WARNING, "POST: Unexpected post code "
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"in previous boot: 0x%02x\n", code);
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#if CONFIG_ELOG
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elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code);
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#if CONFIG_CMOS_POST_EXTRA
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if (extra)
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elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra);
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#endif
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#endif
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}
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}
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#if CONFIG_CMOS_POST_EXTRA
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void post_log_extra(u32 value)
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{
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spin_lock(&cmos_post_lock);
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switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
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case CMOS_POST_BANK_0_MAGIC:
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cmos_write32(CMOS_POST_BANK_0_EXTRA, value);
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break;
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case CMOS_POST_BANK_1_MAGIC:
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cmos_write32(CMOS_POST_BANK_1_EXTRA, value);
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break;
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}
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spin_unlock(&cmos_post_lock);
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}
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void post_log_path(struct device *dev)
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{
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if (dev) {
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/* Encode path into lower 3 bytes */
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u32 path = dev_path_encode(dev);
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/* Upper byte contains the log type */
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path |= CMOS_POST_EXTRA_DEV_PATH << 24;
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post_log_extra(path);
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}
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}
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void post_log_clear(void)
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{
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post_log_extra(0);
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}
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#endif /* CONFIG_CMOS_POST_EXTRA */
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#endif /* !__PRE_RAM__ */
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static void cmos_post_code(u8 value)
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{
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spin_lock(&cmos_post_lock);
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switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
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case CMOS_POST_BANK_0_MAGIC:
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cmos_write(value, CMOS_POST_BANK_0_OFFSET);
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break;
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case CMOS_POST_BANK_1_MAGIC:
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cmos_write(value, CMOS_POST_BANK_1_OFFSET);
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break;
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}
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spin_unlock(&cmos_post_lock);
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}
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#endif /* CONFIG_CMOS_POST */
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void post_code(uint8_t value)
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{
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#if !CONFIG_NO_POST
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#if CONFIG_CONSOLE_POST
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print_emerg("POST: 0x");
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print_emerg_hex8(value);
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print_emerg("\n");
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#endif
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#if CONFIG_CMOS_POST
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cmos_post_code(value);
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#endif
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#if CONFIG_IO_POST
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outb(value, CONFIG_IO_POST_PORT);
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#endif
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#endif
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mainboard_post(value);
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}
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