Vincent Palatin 0f73a129b4 Add Cortex-M0 core support ...

The Cortex-M0 core is based on ARMv6-M instruction set rather than
ARMv7-M as Cortex-M3 and M4.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=none
TEST=run console on STM32F072,
and pass all available unit-tests on target.

Change-Id: I9bdf6637132ba4a3e739d388580a72b4c84e930e
Reviewed-on: https://chromium-review.googlesource.com/188982
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>

2014-03-11 05:52:41 +00:00

..

cortex-m

force the compiler to use a valid register allocation for irq handlers

2014-03-11 05:52:37 +00:00

cortex-m0

Add Cortex-M0 core support

2014-03-11 05:52:41 +00:00

host

force the compiler to use a valid register allocation for irq handlers

2014-03-11 05:52:37 +00:00

nds32

force the compiler to use a valid register allocation for irq handlers

2014-03-11 05:52:37 +00:00