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https://github.com/Telecominfraproject/OpenCellular.git
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It turns out that even when the UART status register returns TX_IDLE
bit set, the transmitter is still active - probably working out the
stop sequence.
So, resetting immediately after TX_EMPTY is asserted causes the last
character to be corrupted on the receiving side.
This patch adds a wait for the duration of transmitting 10 bits at
115200 baud, which should be plenty. Wait loop in capped in case timer
is not running for any reason.
BRANCH=none
BUG=chrome-os-partner:60321
TEST=added code to print out a string and then call cflush() and reset
immediately. The last character is not lost any more, the exact
string is printed.
Change-Id: If386c515d9d9cc63d161fba73e6ed4e70e465136
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/418487
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
172 lines
4.1 KiB
C
172 lines
4.1 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "clock.h"
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#include "common.h"
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#include "gpio.h"
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#include "registers.h"
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#include "system.h"
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#include "task.h"
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#include "uart.h"
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#include "util.h"
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#define USE_UART_INTERRUPTS (!(defined(CONFIG_CUSTOMIZED_RO) && \
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defined(SECTION_IS_RO)))
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struct uartn_interrupts {
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int tx_int;
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int rx_int;
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};
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static struct uartn_interrupts interrupt[] = {
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{GC_IRQNUM_UART0_TXINT, GC_IRQNUM_UART0_RXINT},
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{GC_IRQNUM_UART1_TXINT, GC_IRQNUM_UART1_RXINT},
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{GC_IRQNUM_UART2_TXINT, GC_IRQNUM_UART2_RXINT},
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};
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void uartn_tx_start(int uart)
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{
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if (!uart_init_done())
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return;
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/* If interrupt is already enabled, nothing to do */
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if (GR_UART_ICTRL(uart) & GC_UART_ICTRL_TX_MASK)
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return;
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/* Do not allow deep sleep while transmit in progress */
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disable_sleep(SLEEP_MASK_UART);
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/*
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* Re-enable the transmit interrupt, then forcibly trigger the
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* interrupt. This works around a hardware problem with the
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* UART where the FIFO only triggers the interrupt when its
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* threshold is _crossed_, not just met.
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*/
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/* TODO(crosbug.com/p/33819): Do we need this hack here? Find out. */
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REG_WRITE_MLV(GR_UART_ICTRL(uart), GC_UART_ICTRL_TX_MASK,
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GC_UART_ICTRL_TX_LSB, 1);
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task_trigger_irq(interrupt[uart].tx_int);
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}
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void uartn_tx_stop(int uart)
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{
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/* Disable the TX interrupt */
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REG_WRITE_MLV(GR_UART_ICTRL(uart), GC_UART_ICTRL_TX_MASK,
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GC_UART_ICTRL_TX_LSB, 0);
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/* Re-allow deep sleep */
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enable_sleep(SLEEP_MASK_UART);
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}
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int uartn_tx_in_progress(int uart)
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{
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/* Transmit is in progress unless the TX FIFO is empty and idle. */
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return !(GR_UART_STATE(uart) & (GC_UART_STATE_TXIDLE_MASK |
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GC_UART_STATE_TXEMPTY_MASK));
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}
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void uartn_tx_flush(int uart)
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{
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timestamp_t ts;
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int i;
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/* Wait until TX FIFO is idle. */
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while (uartn_tx_in_progress(uart))
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;
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/*
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* Even when uartn_tx_in_progress() returns false, the chip seems to
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* be still trasmitting, resetting at this point results in an eaten
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* last symbol. Let's just wait some time (required to transmit 10
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* bits at 115200 baud).
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*/
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ts = get_time(); /* Start time. */
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for (i = 0; i < 1000; i++) /* Limit it in case timer is not running. */
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if ((get_time().val - ts.val) > ((1000000 * 10) / 115200))
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return;
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}
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int uartn_tx_ready(int uart)
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{
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/* True if the TX buffer is not completely full */
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return !(GR_UART_STATE(uart) & GC_UART_STATE_TX_MASK);
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}
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int uartn_rx_available(int uart)
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{
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/* True if the RX buffer is not completely empty. */
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return !(GR_UART_STATE(uart) & GC_UART_STATE_RXEMPTY_MASK);
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}
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void uartn_write_char(int uart, char c)
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{
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/* Wait for space in transmit FIFO. */
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while (!uartn_tx_ready(uart))
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;
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GR_UART_WDATA(uart) = c;
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}
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int uartn_read_char(int uart)
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{
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return GR_UART_RDATA(uart);
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}
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void uartn_disable_interrupt(int uart)
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{
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task_disable_irq(interrupt[uart].tx_int);
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task_disable_irq(interrupt[uart].rx_int);
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}
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void uartn_enable_interrupt(int uart)
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{
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task_enable_irq(interrupt[uart].tx_int);
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task_enable_irq(interrupt[uart].rx_int);
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}
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void uartn_enable(int uart)
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{
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/* Enable TX and RX. Disable HW flow control and loopback. */
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GR_UART_CTRL(uart) = 0x03;
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}
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/* Disable TX, RX, HW flow control, and loopback */
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void uartn_disable(int uart)
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{
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GR_UART_CTRL(uart) = 0;
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}
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void uartn_init(int uart)
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{
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long long setting = (16 * (1 << UART_NCO_WIDTH) *
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(long long)CONFIG_UART_BAUD_RATE / PCLK_FREQ);
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/* set frequency */
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GR_UART_NCO(uart) = setting;
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/*
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* Interrupt when RX fifo has anything, when TX fifo <= half
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* empty and reset (clear) both FIFOs
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*/
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GR_UART_FIFO(uart) = 0x63;
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/*
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* To reduce the number of UART RX interrupts on the peripheral UARTS,
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* set the FIFO RXILVL to only trigger rx interrupts every 4 characters.
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*
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* Reset the RX FIFO.
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*/
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if (uart)
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GR_UART_FIFO(uart) |= 0x7;
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/* enable RX interrupts in block */
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/* Note: doesn't do anything unless turned on in NVIC */
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GR_UART_ICTRL(uart) = 0x02;
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#if USE_UART_INTERRUPTS
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/* Enable interrupts for UART */
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uartn_enable_interrupt(uart);
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#endif
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}
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