Duncan Laurie c806e4cc59 skylake: Add GPIO macro for configuring inverted APIC input ...

Add a GPIO macro that allows a pin to be routed to the APIC with
the input inverted.  This allows a normal interrupt to get used as
a GPE during firmware and still be used as a perhiperal interrupt
in the kernel.

BUG=chrome-os-partner:58666
TEST=boot en eve and use TPM IRQ in firmware and OS

Change-Id: I77f727f749fdd5281ff595a9237fe1e634daba96
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17176
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2016-10-28 18:59:46 +02:00

..

acpi

src/acpi: Capitalize ACPI and SATA

2016-07-31 19:25:40 +02:00

arch

arch/x86/acpigen_dsm: Add support for DSM types

2016-10-25 00:13:32 +02:00

commonlib

commonlib: move DIV_ROUND macros from nvidia/tegra

2016-09-07 20:52:42 +02:00

console

Revert "[WIP] console/Kconfig: Calculate COM port base addresses only on x86"

2016-10-18 18:41:16 +02:00

cpu

src/cpu: Fix location for cpu_microcode_blob.bin in COREBOOT CBFS only

2016-10-11 23:36:18 +02:00

device

Kconfig: Update default hex values to start with 0x

2016-10-02 19:08:15 +02:00

drivers

driver/intel/fsp2_0: Reset on invalid stage cache.

2016-10-27 17:01:46 +02:00

ec

ec/lenovo/h8: fix whitespaces/tabs

2016-10-17 22:17:37 +02:00

include

RISCV: Clean up the common architectural code

2016-10-24 20:25:04 +02:00

lib

soc/intel/apollolake: Implement stage cache to improve resume time

2016-10-07 18:18:14 +02:00

mainboard

pcengines/apu1: Add RS485 configuration

2016-10-28 16:56:55 +02:00

northbridge

nb/x4x/gma.c: Remove writes to DP, FDI registers

2016-10-26 22:39:35 +02:00

soc

skylake: Add GPIO macro for configuring inverted APIC input

2016-10-28 18:59:46 +02:00

southbridge

southbridge/nvidia: Remove commented code

2016-10-11 23:33:23 +02:00

superio

winbond/w83627ehg: Remove unnecessary value

2016-10-19 17:31:39 +02:00

vboot

vboot: Stop creating backup space in TPM

2016-10-13 18:22:03 +02:00

vendorcode

vendorcode/intel/fsp: Update UPD headers for FSP 157_10

2016-10-07 19:13:53 +02:00

Kconfig

Kconfig: Update default hex values to start with 0x

2016-10-02 19:08:15 +02:00