Jeenu Viswambharan 17e84eedb2 GIC: Fix setting interrupt configuration ...

- Interrupt configuration is a 2-bit field, so the field shift has to
    be double that of the bit number.

  - Interrupt configuration (level- or edge-trigger) is specified in the
    MSB of the field, not LSB.

Fixes applied to both GICv2 and GICv3 drivers.

Fixes ARM-software/tf-issues#570

Change-Id: Ia6ae6ed9ba9fb0e3eb0f921a833af48e365ba359
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

2018-03-26 09:45:48 +01:00

..

bl1

Fix MISRA rule 8.4 Part 1

2018-02-28 17:19:55 +00:00

bl2

Fix MISRA rule 8.4 Part 1

2018-02-28 17:19:55 +00:00

bl2u

Fix MISRA rule 8.4 in common code

2018-02-28 17:18:46 +00:00

bl31

Merge pull request #1282 from robertovargas-arm/misra-changes

2018-02-28 18:53:30 +00:00

bl32

Introduce the new BL handover interface

2018-02-26 16:31:10 +00:00

common

Rename 'smcc' to 'smccc'

2018-03-21 10:49:27 +00:00

drivers

GIC: Fix setting interrupt configuration

2018-03-26 09:45:48 +01:00

lib

Rename 'smcc' to 'smccc'

2018-03-21 10:49:27 +00:00

plat

Remove sp_min functions from plat_common.c

2018-03-02 16:41:18 +00:00

services

Implement support for SMCCC v1.1

2018-01-29 09:58:57 +00:00

tools_share

Dynamic cfg: Update the tools

2018-02-26 16:31:10 +00:00