Alec Berg 0e402965fa cortex-m0: stm32f0: use RW vector table when running RW code ...

Currently, on stm32f cortex-m0 systems, interrupts are always being
directed to the RO vector table. This can cause strange problems when
running RW software because it is still calling IRQ handlers in the RO
code.

Unfortunately, on cortex-m0 the ability to specify the vector table
location in flash (VTOR register) is optional, and stm32f0 parts do not
have it. Instead, in order to run RW IRQ handlers, at init time, this
CL copies the vector table from flash to the base address of SRAM
(0x20000000), and then selects SRAM to be mapped to 0x00000000 where
the core looks to find the vector table.

BUG=none
BRANCH=none
TEST=Tested on zinger.
- Verified that vector table is copied to SRAM by printing out 48 words
from SRAM base address 0x20000000 in main() and verifying that it matches
the vector table in flash in the disassembly.
- Verified the vector table at SRAM 0x20000000 points to the RW handlers
when in RW and the RO handlers when in RO.
- Also printed out PC in one IRQ handler and verified it was in the
appropriate section of code.

Also, ran on samus_pd and did a sysjump RW to make sure at least one other
system works.

Change-Id: I22aff1b5e0de9b23fd3324f0cbe4f6c45a81967e
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210063
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>

2014-07-29 04:36:44 +00:00

..

cortex-m

better unhandled exception panic without runtime

2014-07-03 02:56:52 +00:00

cortex-m0

cortex-m0: stm32f0: use RW vector table when running RW code

2014-07-29 04:36:44 +00:00

host

Add cprints() and ccprints()

2014-05-21 20:32:17 +00:00

nds32

Add cprints() and ccprints()

2014-05-21 20:32:17 +00:00