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3a0e2a08f5
After reset DPLL_CTRL2 is initialized to 0. Which means some clock disable bits are not set and might cause some hassle later. Set them and close the related TODO. Change-Id: I1a470dff55e317e8119906b3e397f6f2314abcbd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20648 Tested-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
8 lines
250 B
Plaintext
8 lines
250 B
Plaintext
medium DP re-read status if updated bit isn't set
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medium DP honor adjust requests also if training succeeded?
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unknown DP honor SINK_STATUS after training
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low LVDS 8bit colors, data format???
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medium gfxtest take care of our own framebuffer mapping
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