mirror of
https://github.com/Telecominfraproject/OpenCellular.git
synced 2025-12-28 10:45:22 +00:00
c5b90d7e77
First implementation of a low power idle task for the LM4 chip. The low power mode is selected by defining CONFIG_LOW_POWER_IDLE in a board.h file. This commit turns it on for Peppy, Slippy, and Falco only because those are the only boards tested. When using the low power idle task, the chip goes in to deep sleep when it can. Deep sleep disables clocks to most peripherals and puts the onboard flash and RAM into a low power mode. The chip is woken out of deep sleep using the RTC in the hibernate module. Increased the idle task stack size to handle more involved idle task. In board.c, the array of GPIO info can be used to select which GPIO points can wake up the EC from deep sleep. Currenlty selected are the power button, lid open, AC present, PCH_SLP_S3, and PCH_SLP_S5. Additionally the port with the KB scan row GPIO point is also enabled to wake up the EC from deep sleep. Signed-off-by: Alec Berg <alecaberg@chromium.org> BUG=None BRANCH=none TEST=Passes all unit tests. Runs on slippy, peppy, and falco with no noticeable side affects. Verified that the power consumed by the EC is lower when in S3, S5 and G3 by scoping the sense resistor powering the chip. Change-Id: I83fa9a159a4b79201b99f2c32678dc4fc8921726 Reviewed-on: https://chromium-review.googlesource.com/172183 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org>
85 lines
2.6 KiB
C
85 lines
2.6 KiB
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
|
|
* Use of this source code is governed by a BSD-style license that can be
|
|
* found in the LICENSE file.
|
|
*/
|
|
|
|
/* Clocks and power management settings */
|
|
|
|
#ifndef __CROS_EC_CLOCK_H
|
|
#define __CROS_EC_CLOCK_H
|
|
|
|
#include "common.h"
|
|
|
|
/**
|
|
* Set the CPU clocks and PLLs.
|
|
*/
|
|
void clock_init(void);
|
|
|
|
/**
|
|
* Return the current clock frequency in Hz.
|
|
*/
|
|
int clock_get_freq(void);
|
|
|
|
/**
|
|
* Enable or disable clock for a module.
|
|
*
|
|
* Note that if the module requires a higher system clock speed than the
|
|
* current system clock speed, the entire system clock will be increased
|
|
* to allow the module to operate.
|
|
*
|
|
* When a module is disabled, the system clock will be reduced to the highest
|
|
* clock required by the remaining enabled modules.
|
|
*
|
|
* @param module The module for which we need to enable/disable its
|
|
* clock.
|
|
* @param enable Enable clock if non-zero; disable if zero.
|
|
*/
|
|
void clock_enable_module(enum module_id module, int enable);
|
|
|
|
/**
|
|
* Enable or disable the PLL.
|
|
*
|
|
* @param enable Enable PLL if non-zero; disable if zero.
|
|
* @param notify Notify other modules of the PLL change. This should
|
|
* be 1 unless you're briefly turning on the PLL to work
|
|
* around a chip errata at init time.
|
|
*/
|
|
void clock_enable_pll(int enable, int notify);
|
|
|
|
/**
|
|
* Wait for a number of clock cycles.
|
|
*
|
|
* Simple busy waiting for use before clocks/timers are initialized.
|
|
*
|
|
* @param cycles Number of cycles to wait.
|
|
*/
|
|
void clock_wait_cycles(uint32_t cycles);
|
|
|
|
/* Clock gate control modes for clock_enable_peripheral() */
|
|
#define CGC_MODE_RUN (1 << 0)
|
|
#define CGC_MODE_SLEEP (1 << 1)
|
|
#define CGC_MODE_DSLEEP (1 << 2)
|
|
#define CGC_MODE_ALL (CGC_MODE_RUN | CGC_MODE_SLEEP | CGC_MODE_DSLEEP)
|
|
|
|
/**
|
|
* Enable clock to peripheral by setting the CGC register pertaining
|
|
* to run, sleep, and/or deep sleep modes.
|
|
*
|
|
* @param offset Offset of the peripheral. See enum clock_gate_offsets.
|
|
* @param mask Bit mask of the bits within CGC reg to set.
|
|
* @param mode Which mode(s) to enable the clock for
|
|
*/
|
|
void clock_enable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode);
|
|
|
|
/**
|
|
* Disable clock to peripheral by setting the CGC register pertaining
|
|
* to run, sleep, and/or deep sleep modes.
|
|
*
|
|
* @param offset Offset of the peripheral. See enum clock_gate_offsets.
|
|
* @param mask Bit mask of the bits within CGC reg to clear.
|
|
* @param mode Which mode(s) to enable the clock for
|
|
*/
|
|
void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode);
|
|
|
|
#endif /* __CROS_EC_CLOCK_H */
|