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748154d55f
Preventing instruction fetch from RAM for Link except iram.text, which is used for hibernation. Stm32 on Snow does not support MPU. Tested on Link using commands 'crash nxtext/nxdata/nxstack', which run code from .iram.text, .data section, and the stack, respectively: ... RAM locked. Exclusion 20005980-200059a0 ... > crash nxtext Running from 20005984 > crash nxdata === PROCESS EXCEPTION: 04 ====== xPSR: 61000000 === r0 :00000000 r1 :0000dff2 r2 :00000005 r3 :0000086d r4 :00000000 r5 :00000032 r6 :2000544c r7 :00000000 r8 :00000000 r9 :20005456 r10:00000000 r11:00000000 r12:20005961 sp :20002748 lr :000008d7 pc :20005960 Instruction access violation mmfs = 1, shcsr = 70001, hfsr = 0, dfsr = 0 =========== Process Stack Contents =========== 200027b0: 0000086d 00000002 0000d504 00009f27 200027c0: 2000544c 20005452 00000000 00000000 200027d0: 00000000 00000000 00000000 00000000 200027e0: 00000000 00000000 00000000 00000cbb Rebooting... > crash nxstack === PROCESS EXCEPTION: 04 ====== xPSR: 20000200 === r0 :00000070 r1 :00000047 r2 :00000000 r3 :200027a8 r4 :00000000 r5 :00000001 r6 :2000544c r7 :00000000 r8 :00000000 r9 :20005456 r10:00000000 r11:00000000 r12:00000002 sp :20002740 lr :00000913 pc :200027ac Instruction access violation mmfs = 1, shcsr = 70001, hfsr = 0, dfsr = 0 =========== Process Stack Contents =========== 200027ac: 00000070 00000047 00000002 0000d57c 200027bc: 00009f9f 2000544c 20005452 00000000 200027cc: 00000000 00000000 00000000 00000000 200027dc: 00000000 00000000 00000000 00000000 Rebooting... BUG=chrome-os-partner:16904 BRANCH=master TEST=stated above Change-Id: I7c6593c527f29609442f33550f9d16755f32297c Signed-off-by: Daisuke Nojiri <dnojiri@google.com> Reviewed-on: https://chromium-review.googlesource.com/51337 Reviewed-by: Randall Spangler <rspangler@chromium.org>
85 lines
2.2 KiB
C
85 lines
2.2 KiB
C
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* MPU module for Cortex-M3 */
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#ifndef __CROS_EC_MPU_H
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#define __CROS_EC_MPU_H
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#include "common.h"
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#define MPU_TYPE REG32(0xe000ed90)
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#define MPU_CTRL REG32(0xe000ed94)
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#define MPU_NUMBER REG32(0xe000ed98)
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#define MPU_BASE REG32(0xe000ed9c)
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#define MPU_SIZE REG16(0xe000eda0)
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#define MPU_ATTR REG16(0xe000eda2)
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#define MPU_CTRL_PRIVDEFEN (1 << 2)
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#define MPU_CTRL_HFNMIENA (1 << 1)
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#define MPU_CTRL_ENABLE (1 << 0)
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#define MPU_ATTR_NX (1 << 12)
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#define MPU_ATTR_NOACCESS (0 << 8)
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#define MPU_ATTR_FULLACCESS (3 << 8)
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/* Suggested in table 3-6 of Stellaris LM4F232H5QC Datasheet and table 38 of
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* STM32F10xxx Cortex-M3 programming manual for internal sram. */
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#define MPU_ATTR_INTERNALSRAM 6
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/**
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* Configure a region
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*
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* region: Number of the region to update
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* addr: Base address of the region
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* size: Size of the region in bytes
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* attr: Attribute of the region. Current value will be overwritten if enable
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* is set.
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* enable: Enables the region if non zero. Otherwise, disables the region.
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*
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* Returns EC_SUCCESS on success or EC_ERROR_INVAL if a parameter is invalid.
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*/
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int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size,
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uint16_t attr, uint8_t enable);
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/**
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* Set a region non-executable.
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*
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* region: number of the region
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* addr: base address of the region
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* size: size of the region in bytes
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*/
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int mpu_nx_region(uint8_t region, uint32_t addr, uint32_t size);
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/**
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* Enable MPU */
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void mpu_enable(void);
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/**
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* Returns the value of MPU type register
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*
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* Bit fields:
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* [15:8] Number of the data regions implemented or 0 if MPU is not present.
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* [1] 0: unified (no distinction between instruction and data)
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* 1: separated
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*/
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uint32_t mpu_get_type(void);
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/* Location of iram.text */
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extern char __iram_text_start;
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extern char __iram_text_end;
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/**
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* Lock down RAM
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*/
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int mpu_protect_ram(void);
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/**
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* Initialize MPU.
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* It disables all regions if MPU is implemented. Otherwise, returns
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* EC_ERROR_UNIMPLEMENTED.
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*/
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int mpu_pre_init(void);
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#endif /* __CROS_EC_MPU_H */
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