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36df8427f4
Without this configuration defined the board assumes battery only mode for G3->S5 boot up power sequence and thereby waits for power button press. BUG=b:76230069;b:75974377 BRANCH=None TEST=On yorp, with battery and external power connected reboot on EC console boot the SoC to S0. Verify on both ports. Change-Id: I837b7f99bd3c238ce74e394c773169d703ad9392 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1008247 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>