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3405c79584
This change is a safegaurd to ensure that TPM register data is always placed in the correct location in the HW read I2CS fifo. It is only checked for 1 or 4 byte regsiter reads. Because of the way in which a TPM command is sent and the response is read, there are multiple reads of the STS register prior to reading the TPM fifo register. Therefore ensuring the fifo has zero depth when 1 or 4 byte regsiter reads, improves the robustness of the design. Added a counter to track the number of times the fifo is adjusted and a new console command 'i2cs disp|rst' to display the count and reset it to 0 if desired. Removed section in code for TPM fifo register reads intended to handle the case where there was a mismatch between how many bytes were copied into the fifo and the number read by the host. Since the burstcount field in the status register always contains a valid amount of data that can be read by the host, there should not be cases where the host reads less data than was copied from the TPM fifo register. In the unexpected cases where the host may not drain all of the I2CS read fifo data during a TPM register read, the I2CS fifo depth will be corrected the next time that it reads either the access or STS register which happens prior to the start of any TPM transaction. BRANCH=none BUG=chrome-os-partner:57338,chrome-os-partner:59191 TEST=manual Booted Reef and verfied that TPM functionality is working. Change-Id: I065a55e64bbcc0cb3357a2bd83447a05400b8899 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/382689 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>