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https://github.com/Telecominfraproject/OpenCellular.git
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34f2264227
Adds the SPI master driver with support for both SPI masters with support for using GPIOs as chip selects or using the hardware's dedicated chip selects. Note this has not been enabled in the cr50 board. BRANCH=none BUG=none TEST=verified through use of the SPI_FLASH module on cr51 Change-Id: I88719f8d03e217ab44249172b1340011fdcfdad5 Signed-off-by: Ewout van Bekkum <ewout@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/317329 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
111 lines
2.8 KiB
C
111 lines
2.8 KiB
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* SPI interface for Chrome EC */
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#ifndef __CROS_EC_SPI_H
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#define __CROS_EC_SPI_H
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/*
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* SPI Clock polarity and phase mode (0 - 3)
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* @code
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* clk mode | POL PHA
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* ---------+--------
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* 0 | 0 0
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* 1 | 0 1
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* 2 | 1 0
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* 3 | 1 1
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* ---------+--------
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* @endcode
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*/
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enum spi_clock_mode {
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SPI_CLOCK_MODE0 = 0,
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SPI_CLOCK_MODE1 = 1,
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SPI_CLOCK_MODE2 = 2,
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SPI_CLOCK_MODE3 = 3
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};
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struct spi_device_t {
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/*
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* SPI port the device is connected to.
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* On some architecture, this is SPI master port index,
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* on other the SPI port index directly.
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*/
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uint8_t port;
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/*
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* Clock divisor to talk to SPI device.
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* If several devices share the same port, we select the lowest speed.
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*/
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uint8_t div;
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/* gpio used for chip selection. */
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enum gpio_signal gpio_cs;
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};
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extern const struct spi_device_t spi_devices[];
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extern const unsigned int spi_devices_used;
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/*
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* The first port in spi_devices defines the port to access the SPI flash.
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* The first gpio defines the CS GPIO to access the flash,
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* if used.
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*/
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#define SPI_FLASH_DEVICE (&spi_devices[0])
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/*
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* Enable / disable the SPI port. When the port is disabled, all its I/O lines
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* are high-Z so the EC won't interfere with other devices on the SPI bus.
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*
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* @param port port id to work on.
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* @param enable 1 to enable the port, 0 to disable it.
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*/
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int spi_enable(int port, int enable);
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/* Issue a SPI transaction. Assumes SPI port has already been enabled.
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*
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* Transmits <txlen> bytes from <txdata>, throwing away the corresponding
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* received data, then transmits <rxlen> dummy bytes, saving the received data
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* in <rxdata>.
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*
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* @param spi_device the SPI device to use
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* @param txdata buffer to transmit
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* @param txlen number of bytes in txdata.
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* @param rxdata receive buffer.
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* @param rxlen number of bytes in rxdata.
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*/
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int spi_transaction(const struct spi_device_t *spi_device,
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const uint8_t *txdata, int txlen,
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uint8_t *rxdata, int rxlen);
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/* Similar to spi_transaction(), but hands over to DMA for reading response.
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* Must call spi_transaction_flush() after this to make sure the response is
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* received.
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*/
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int spi_transaction_async(const struct spi_device_t *spi_device,
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const uint8_t *txdata, int txlen,
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uint8_t *rxdata, int rxlen);
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/* Wait for async response received */
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int spi_transaction_flush(const struct spi_device_t *spi_device);
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#ifdef CONFIG_SPI
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/**
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* Called when the NSS level changes, signalling the start or end of a SPI
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* transaction.
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*
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* @param signal GPIO signal that changed
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*/
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void spi_event(enum gpio_signal signal);
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#else
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static inline void spi_event(enum gpio_signal signal)
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{
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}
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#endif
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#endif /* __CROS_EC_SPI_H */
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