Brandon Breitenstein 7692807f4f vendorcode/intel/fsp: Update UPD headers for FSP 157_10 ...

These header files contain a few new UPDs. The EnableS3Heci2
UPD will be used to save ~100ms from the S3 resume time on
Apollolake chrome platforms.

BUG=chrome-os-partner:58121
BRANCH=none
TEST=built coreboot for reef and verified no regressions

Change-Id: I1f324d00237c7150697800258a2f7b7eed856417
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/16869
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

2016-10-07 19:13:53 +02:00

..

amd

vendorcode/amd/pi/Kconfig: update AGESA_BINARY_PI_LOCATION to hex

2016-10-02 19:08:33 +02:00

google

Kconfig: Update default hex values to start with 0x

2016-10-02 19:08:15 +02:00

intel

vendorcode/intel/fsp: Update UPD headers for FSP 157_10

2016-10-07 19:13:53 +02:00

siemens

intel/i210: Change API for function mainboard_get_mac_address()

2016-07-05 06:27:44 +02:00

Makefile.inc

vendorcode/siemens: Add hwilib for Siemens specific info struct

2016-04-28 08:15:47 +02:00