Aaron Durbin 38613d079d soc/intel/skylake: provide poweroff() implementation ...

Implement poweroff() by putting the chipset into ACPI S5 state.

BUG=chrome-os-partner:54977

Change-Id: I9288dcee13347a8aa3f822ca3d75148ba2792859
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15688
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)

2016-07-15 08:36:12 +02:00

..

acpi

arch/x86: provide common Intel ACPI hardware definitions

2016-07-15 08:31:21 +02:00

arch

arch/x86: provide common Intel ACPI hardware definitions

2016-07-15 08:31:21 +02:00

commonlib

region: Add writeat and eraseat support

2016-06-24 20:48:12 +02:00

console

console/post: be explicit about conditional cmos_post_log() compiling

2016-05-25 18:04:11 +02:00

cpu

intel post-car: Consolidate choose_top_of_stack()

2016-07-10 11:16:07 +02:00

device

device: i2c: Add support for I2C bus operations

2016-06-09 17:05:40 +02:00

drivers

drivers/intel/fsp1_1: align on using ACPI_Sx definitions

2016-07-15 08:31:09 +02:00

ec

ec/google/chromeec: provide common SMI handler helpers

2016-07-15 08:35:29 +02:00

include

lib: add poweroff() declaration

2016-07-15 08:35:15 +02:00

lib

lib/version: Correct whitespace alignment

2016-07-15 00:10:50 +02:00

mainboard

mainboards/apollolake: use common Chrome EC SMI helpers

2016-07-15 08:35:59 +02:00

northbridge

nb/intel/pineview/northbridge.c: Remove legacy_hole_size_k declaration

2016-07-14 00:02:24 +02:00

soc

soc/intel/skylake: provide poweroff() implementation

2016-07-15 08:36:12 +02:00

southbridge

southbridge/intel/fsp_bd82x6x: use common Intel ACPI hardware definitions

2016-07-15 08:34:46 +02:00

superio

sio/winbond/w83667hg-a: Add pinmux defines for UART B

2016-05-29 19:34:54 +02:00

vendorcode

chromeos: Fill in the firmware id (RO, RW A, RW B) FMAP sections

2016-07-15 00:40:19 +02:00

Kconfig

Romstage spinlocks require EARLY_CBMEM_INIT

2016-07-10 04:03:31 +02:00