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336db102e6
The high speed clock does not run when cr50 is in sleep. The low speed timers do run in sleep and deep sleep. This change modifies the hwtimer to use the low speed timers instead of the high speed ones. With this change the system timer frequency is reduced and will only tick once every 4 mircoseconds. Now the system will resume from sleep whenever an event is scheduled, but still wont resume from deep sleep. BUG=chromium:635620 BRANCH=none TEST=manual Disable sleep add a function that prints something every second. Verify the rollover works at ~4295s. Change the system time using force_time. Re-enable sleep and reduce the sleep delays in board/cr50/board.c and chip/g/idle.ci so cr50 will go to sleep more quickly. Verify the rollover and changing system time works. check that cr50 can go into deep sleep and that the print statement wont wake it up. Put the system into deep sleep. Use a wake pin to make it resume. Verify it can be put back into deep sleep without the wakepin interrupt constantly triggering. Change-Id: I70bbc9312cd172661de53334d256949ebab6b5e9 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/376800
156 lines
4.0 KiB
C
156 lines
4.0 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "common.h"
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#include "hooks.h"
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#include "hwtimer.h"
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#include "registers.h"
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#include "task.h"
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#include "util.h"
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/* The frequency of timerls is 256k so there are about 4usec/tick */
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#define USEC_PER_TICK 4
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/*
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* Scale the maximum number of ticks so that it will only count up to the
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* equivalent of 0xffffffff usecs.
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*/
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#define TIMELS_MAX (0xffffffff / USEC_PER_TICK)
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#define SOURCE(field) TIMER0_##field
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#define EVENT(field) TIMER1_##field
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static inline uint32_t ticks_to_usecs(uint32_t ticks)
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{
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return ticks * USEC_PER_TICK;
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}
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static inline uint32_t usec_to_ticks(uint32_t next_evt_us)
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{
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return next_evt_us / USEC_PER_TICK;
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}
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uint32_t __hw_clock_event_get(void)
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{
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/* At what time will the next event fire? */
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return __hw_clock_source_read() +
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ticks_to_usecs(GREG32(TIMELS, EVENT(VALUE)));
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}
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void __hw_clock_event_clear(void)
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{
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/* one-shot, 32-bit, timer & interrupts disabled, 1:1 prescale */
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GWRITE_FIELD(TIMELS, EVENT(CONTROL), ENABLE, 0);
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/* Disable interrupts */
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GWRITE(TIMELS, EVENT(IER), 0);
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/* Clear any pending interrupts */
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GWRITE(TIMELS, EVENT(WAKEUP_ACK), 1);
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GWRITE(TIMELS, EVENT(IAR), 1);
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}
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void __hw_clock_event_set(uint32_t deadline)
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{
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uint32_t event_time;
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__hw_clock_event_clear();
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/* How long from the current time to the deadline? */
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event_time = (deadline - __hw_clock_source_read());
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/* Convert event_time to ticks rounding up */
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GREG32(TIMELS, EVENT(LOAD)) =
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((uint64_t)(event_time + USEC_PER_TICK - 1) / USEC_PER_TICK);
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/* Enable the timer & interrupts */
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GWRITE(TIMELS, EVENT(IER), 1);
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GWRITE_FIELD(TIMELS, EVENT(CONTROL), ENABLE, 1);
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}
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/*
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* Handle event matches. It's priority matches the HW rollover irq to prevent
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* a race condition that could lead to a watchdog timeout if preempted after
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* the get_time() call in process_timers().
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*/
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void __hw_clock_event_irq(void)
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{
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__hw_clock_event_clear();
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process_timers(0);
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}
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DECLARE_IRQ(GC_IRQNUM_TIMELS0_TIMINT1, __hw_clock_event_irq, 1);
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uint32_t __hw_clock_source_read(void)
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{
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/*
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* Return the current time in usecs. Since the counter counts down,
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* we have to invert the value.
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*/
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return ticks_to_usecs(TIMELS_MAX - GREG32(TIMELS, SOURCE(VALUE)));
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}
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void __hw_clock_source_set(uint32_t ts)
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{
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GREG32(TIMELS, SOURCE(LOAD)) = (0xffffffff - ts) / USEC_PER_TICK;
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}
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/* This handles rollover in the HW timer */
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void __hw_clock_source_irq(void)
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{
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/* Clear the interrupt */
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GWRITE(TIMELS, SOURCE(WAKEUP_ACK), 1);
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GWRITE(TIMELS, SOURCE(IAR), 1);
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/* Reset the load value */
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GREG32(TIMELS, SOURCE(LOAD)) = TIMELS_MAX;
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process_timers(1);
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}
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DECLARE_IRQ(GC_IRQNUM_TIMELS0_TIMINT0, __hw_clock_source_irq, 1);
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int __hw_clock_source_init(uint32_t start_t)
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{
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/* Verify the contents of CC_TRIM are valid */
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ASSERT(GR_FUSE(RC_RTC_OSC256K_CC_EN) == 0x5);
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/* Initialize RTC to 256kHz */
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GWRITE_FIELD(RTC, CTRL, X_RTC_RC_CTRL,
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GR_FUSE(RC_RTC_OSC256K_CC_TRIM));
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/* Configure timer1 */
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GREG32(TIMELS, EVENT(LOAD)) = TIMELS_MAX;
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GREG32(TIMELS, EVENT(RELOADVAL)) = TIMELS_MAX;
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GWRITE_FIELD(TIMELS, EVENT(CONTROL), WRAP, 1);
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GWRITE_FIELD(TIMELS, EVENT(CONTROL), RELOAD, 0);
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GWRITE_FIELD(TIMELS, EVENT(CONTROL), ENABLE, 0);
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/* Configure timer0 */
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GREG32(TIMELS, SOURCE(RELOADVAL)) = TIMELS_MAX;
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GWRITE_FIELD(TIMELS, SOURCE(CONTROL), WRAP, 1);
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GWRITE_FIELD(TIMELS, SOURCE(CONTROL), RELOAD, 1);
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/* Event timer disabled */
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__hw_clock_event_clear();
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/* Clear any pending interrupts */
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GWRITE(TIMELS, SOURCE(WAKEUP_ACK), 1);
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/* Force the time to whatever we're told it is */
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__hw_clock_source_set(start_t);
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/* HW Timer enabled, periodic, interrupt enabled, 32-bit, wrapping */
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GWRITE_FIELD(TIMELS, SOURCE(CONTROL), ENABLE, 1);
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/* Enable source timer interrupts */
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GWRITE(TIMELS, SOURCE(IER), 1);
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/* Here we go... */
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task_enable_irq(GC_IRQNUM_TIMELS0_TIMINT0);
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task_enable_irq(GC_IRQNUM_TIMELS0_TIMINT1);
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/* Return the Event timer IRQ number (NOT the HW timer IRQ) */
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return GC_IRQNUM_TIMELS0_TIMINT1;
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}
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