Nico Huber 6197b76988 cpu/x86/mtrr: Prepare for ROM_SIZE > 16MiB ...

Most, if not all, chipsets have MMIO between 0xfe000000 and 0xff000000.
So don't try to cache more than 16MiB of the ROM. It's also common that
at most 16MiB are memory mapped.

Change-Id: I5dfa2744190a34c56c86e108a8c50dca9d428268
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26567
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2018-05-31 15:09:30 +00:00

..

amd

Remove AMD K8 cpu and northbridge support

2018-05-31 03:42:11 +00:00

intel

intel: Use MSR_EBC_FREQUENCY_ID instead of 0x2c

2017-12-11 01:10:51 +00:00

x86

cpu/x86/mtrr: Prepare for ROM_SIZE > 16MiB

2018-05-31 15:09:30 +00:00

cpu.h

Rename __attribute__((packed)) --> __packed

2017-07-13 19:45:59 +00:00