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bb27b96f13
Faults should be enabled, otherwise we just get a hard fault whenever they occur. BUG=chrome-os-partner:10146 TEST=manual: build and boot on snow; cause a fault and see that it is reported correctly in the panic message, rather than just a hard fault. Also tested on link, 'rw 1': > rw 1 === EXCEPTION: 06 ====== xPSR: 01000000 =========== r0 :0000000b r1 :00000041 r2 :00000001 r3 :20003720 r4 :00000000 r5 :0000bbb4 r6 :2000371c r7 :00000002 r8 :00000000 r9 :20003721 r10:00000000 r11:00000000 r12:00000000 sp :200019a0 lr :00004ad1 pc :000054f6 Unaligned mmfs = 01000000, shcsr = 00070008, hfsr = 00000000, dfsr = 00000000 Time: 0x00000000006f0938 us Deadline: 0x00000000006ec3d4 -> -0.017764 s from now Active timers: Tsk 1 0x000000000072bc1e -> 0.242406 Tsk 4 0x00000000006ec3d4 -> -0.017764 Tsk 5 0x00000000007a2333 -> 0.727547 Tsk 6 0x00000000007a2193 -> 0.727131 Tsk 7 0x00000000007a1fd9 -> 0.726689 Tsk 9 0x0000000000eeb452 -> 8.366874 Task Ready Name Events Time (s) 0 R << idle >> 00000000 6.854007 1 WATCHDOG 00000000 0.000442 2 VBOOTHASH 00000000 0.286203 3 LIGHTBAR 00000000 0.018957 4 POWERSTATE 00000000 0.020656 5 TEMPSENSOR 00000000 0.000851 6 THERMAL 00000000 0.000643 7 PWM 00000000 0.000243 8 TYPEMATIC 00000000 0.000015 9 X86POWER 00000000 0.010582 10 I8042CMD 00000000 0.000015 11 HOSTCMD 00000000 0.000014 12 R CONSOLE 00000000 0.000336 13 POWERBTN 00000000 0.003883 14 KEYSCAN 00000000 0.000297 Rebooting... Change-Id: I95a4a7fae14359aa4e2b645d2110f91161e7df88 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/26170
54 lines
1.6 KiB
C
54 lines
1.6 KiB
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* Registers map and defintions for Cortex-MLM4x processor
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*/
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#ifndef __CPU_H
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#define __CPU_H
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#include <stdint.h>
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/* Macro to access 32-bit registers */
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#define CPUREG(addr) (*(volatile uint32_t*)(addr))
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/* Nested Vectored Interrupt Controller */
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#define CPU_NVIC_EN(x) CPUREG(0xe000e100 + 4 * (x))
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#define CPU_NVIC_DIS(x) CPUREG(0xe000e180 + 4 * (x))
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#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280 + 4 * (x))
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#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x))
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#define CPU_NVIC_APINT CPUREG(0xe000ed0c)
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#define CPU_NVIC_SWTRIG CPUREG(0xe000ef00)
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#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10)
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#define CPU_NVIC_CCR CPUREG(0xe000ed14)
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#define CPU_NVIC_SHCSR CPUREG(0xe000ed24)
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#define CPU_NVIC_MMFS CPUREG(0xe000ed28)
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#define CPU_NVIC_HFSR CPUREG(0xe000ed2c)
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#define CPU_NVIC_DFSR CPUREG(0xe000ed30)
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#define CPU_NVIC_MFAR CPUREG(0xe000ed34)
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#define CPU_NVIC_BFAR CPUREG(0xe000ed38)
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enum {
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CPU_NVIC_MMFS_BFARVALID = 1 << 15,
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CPU_NVIC_MMFS_MFARVALID = 1 << 7,
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CPU_NVIC_CCR_DIV_0_TRAP = 1 << 4,
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CPU_NVIC_CCR_UNALIGN_TRAP = 1 << 3,
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CPU_NVIC_HFSR_DEBUGEVT = 1UL << 31,
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CPU_NVIC_HFSR_FORCED = 1 << 30,
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CPU_NVIC_HFSR_VECTTBL = 1 << 1,
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CPU_NVIC_SHCSR_MEMFAULTENA = 1 << 16,
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CPU_NVIC_SHCSR_BUSFAULTENA = 1 << 17,
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CPU_NVIC_SHCSR_USGFAULTENA = 1 << 18,
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};
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/* Set up the cpu to detect faults */
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void cpu_init(void);
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#endif /* __CPU_H */
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