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ae15dc8ce5
This allows us to use the two SPI ports as SPI master. Also, to save CPU time on reading large amount of data, let's add an async interface for SPI transaction. BUG=chrome-os-partner:29805 TEST=Read manufacturer ID from SPI flash with sync/async interface BRANCH=None Change-Id: I427f4215602cccc55c4151f4116226b1e0ccc15e Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/204719
49 lines
1.4 KiB
C
49 lines
1.4 KiB
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* SPI interface for Chrome EC */
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#ifndef __CROS_EC_SPI_H
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#define __CROS_EC_SPI_H
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/* Enable / disable the SPI port. When the port is disabled, all its I/O lines
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* are high-Z so the EC won't interfere with other devices on the SPI bus. */
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int spi_enable(int enable);
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/* Issue a SPI transaction. Assumes SPI port has already been enabled.
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* Transmits <txlen> bytes from <txdata>, throwing away the corresponding
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* received data, then transmits <rxlen> dummy bytes, saving the received data
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* in <rxdata>. */
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int spi_transaction(const uint8_t *txdata, int txlen,
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uint8_t *rxdata, int rxlen);
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/* Similar to spi_transaction(), but hands over to DMA for reading response.
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* Must call spi_transaction_flush() after this to make sure the response is
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* received.
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*/
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int spi_transaction_async(const uint8_t *txdata, int txlen,
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uint8_t *rxdata, int rxlen);
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/* Wait for async response received */
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int spi_transaction_flush(void);
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#ifdef CONFIG_SPI
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/**
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* Called when the NSS level changes, signalling the start or end of a SPI
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* transaction.
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*
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* @param signal GPIO signal that changed
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*/
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void spi_event(enum gpio_signal signal);
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#else
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static inline void spi_event(enum gpio_signal signal)
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{
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}
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#endif
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#endif /* __CROS_EC_SPI_H */
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