Shawn Nematbakhsh 1bdf8584bb npcx: flash: Use common code for SPI flash protect reg translation ...

Common code is more flexible and supports more parts, so delete the
npcx-only register translation code.

BUG=chrome-os-partner:60029
BRANCH=gru
TEST=Manual on gru, run 'flashrom -p ec --wp-enable' and check that 0x28
gets written to SR1, which matches our desired 'protect botton 128KB',
according to the datasheet. Also run 'flashrom -p ec --erase' then read
back EC SPI contents, verify ROM is erased except for first 128KB
region.

Change-Id: I526401997ff7ec77f2a6047a4a9af74a671ed69a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/413228
Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 43634d36d273887b1f2349c333a7b4b229a83365)
Reviewed-on: https://chromium-review.googlesource.com/415498
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>

2016-12-01 19:59:09 -08:00

..

board.c

pwm: Add PWM_CONFIG_DSLEEP config flag

2016-04-27 23:58:04 -07:00

board.h

npcx: flash: Use common code for SPI flash protect reg translation

2016-12-01 19:59:09 -08:00

build.mk

npcx: Add CHIP_VARIANT variant for different versions of npcx ec.

2016-03-05 11:36:32 -08:00

ec.tasklist

nuc: Add all IC specific drivers of NPCX5M5G

2015-01-14 03:16:10 +00:00

gpio.inc

npcx: Add 1.8V IO support for some GPIOs and I2C pins.

2016-03-05 04:03:23 -08:00