Ronald G. Minnich 45f6c5e3d4 add cpureginit to romcc code. ...

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2006-04-10 16:40:19 +00:00

..

arch

new cache_as_ram support

2006-04-03 20:38:34 +00:00

boot

these were factored out.

2005-11-17 13:45:46 +00:00

config

new cache_as_ram support

2006-04-03 20:38:34 +00:00

console

1201_ht_bus0_dev0_fidvid_core.diff

2005-12-02 21:52:30 +00:00

cpu

add cpureginit to romcc code.

2006-04-10 16:40:19 +00:00

devices

new cache_as_ram support

2006-04-03 20:38:34 +00:00

drivers

serverworks HT1000/HT2000, bcm5785/5780 support

2006-02-16 17:22:19 +00:00

include

add cpureginit to romcc code.

2006-04-10 16:40:19 +00:00

lib

Updated ep405pc to latest config system.

2005-07-20 18:28:12 +00:00

mainboard

add cpureginit to romcc code.

2006-04-10 16:40:19 +00:00

northbridge

add support for GLIUInit()

2006-04-07 16:55:20 +00:00

pc80

implement io based udelay function for all mainboards that lack an apic

2005-12-04 17:50:32 +00:00

pmc/altimus/mpc7410

changes to support new ppc arch

2005-10-20 01:44:21 +00:00

ram

- Adds support for the Advantech eval board. Configuration was produced

2006-04-01 04:10:44 +00:00

sdram

1201_ht_bus0_dev0_fidvid_core.diff

2005-12-02 21:52:30 +00:00

southbridge

15->11 for device num

2006-04-07 20:35:39 +00:00

stream

Some compilation issue fix for PPC970 port

2005-10-21 00:52:52 +00:00

superio

rename files

2006-02-24 17:23:46 +00:00