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86c7e2e90a
The serial console works. Nothing else is implemented yet. BUG=none BRANCH=ToT TEST=make buildall -j To build, make BOARD=cr50 hex Testing the result requires a development board. I have one. It works with HW revision m3.dist_20140918_094011 Change-Id: I718d93572d315d13e96ef6f296c3c2796e928e66 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/226268 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
43 lines
1.4 KiB
C
43 lines
1.4 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CONFIG_STD_FLASH_H
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#define __CROS_EC_CONFIG_STD_FLASH_H
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/* RO firmware must start at beginning of flash */
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#define CONFIG_FW_RO_OFF 0
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/*
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* The EC uses the one bank of flash to emulate a SPI-like write protect
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* register with persistent state.
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*/
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#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
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#ifdef CONFIG_PSTATE_AT_END
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/* PSTATE is at end of flash */
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#define CONFIG_FW_RO_SIZE CONFIG_FW_IMAGE_SIZE
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#define CONFIG_FW_PSTATE_OFF (CONFIG_FLASH_PHYSICAL_SIZE \
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- CONFIG_FW_PSTATE_SIZE)
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/* Don't claim PSTATE is part of flash */
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#define CONFIG_FLASH_SIZE CONFIG_FW_PSTATE_OFF
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#else
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/* PSTATE immediately follows RO, in the first half of flash */
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#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE \
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- CONFIG_FW_PSTATE_SIZE)
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#define CONFIG_FW_PSTATE_OFF CONFIG_FW_RO_SIZE
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#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE
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#endif
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/* Either way, RW firmware is one firmware image offset from the start */
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#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE
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#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE
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/* TODO(crosbug.com/p/23796): why 2 sets of configs with the same numbers? */
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#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF
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#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_RO_SIZE
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#endif /* __CROS_EC_CONFIG_STD_FLASH_H */
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